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Signal Descriptions
A.1
Signal properties and requirements
A-2
To ensure ease of integration of the ETB11 into embedded applications, and to simplify
synthesis flow, the following design techniques have been used:
•
a single rising edge clock times all activity
•
all signals and buses are unidirectional
•
all inputs are required to be synchronous to the relevant clock (CLK, DBGTCK,
or HCLK).
These techniques simplify the definition of the top-level ETB11 signals because all
outputs change from the rising edge and all inputs are sampled with the rising edge of
the clock. In addition, all signals are either input or output only. Bidirectional signals
are not used.
Note
You must use external logic to synchronize asynchronous signals (for example,
interrupt sources) before applying them to the ETB11.
Copyright © 2002, 2003 ARM Limited. All rights reserved.
ARM DDI 0275D
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