Control Logic; Figure 2-2 Trace Capture Operation - ARM ETB11 Technical Reference Manual

Functional Description
2.3

Control logic

2-6
Control logic monitors the TraceCaptEn signal, the status flags, and the DataValid
signal from the Data Formatter. The logic enables a RAM write access cycle when there
is valid data and trace capture is active. Trace capture is active while the TraceCaptEn
signal is asserted and TrgDelayCounter is nonzero.
TraceCaptEn directly selects RAM write or read mode and the RAM address source.
When TraceCaptEn is asserted all RAM access cycles are writes using the write
pointer as the address. When TraceCaptEn is deasserted, RAM accesses are controlled
by the AHB interface when SoftwareCntl (control register bit 4) is HIGH and SWEN
is HIGH. Otherwise, all access cycles are reads using the RAM Read Pointer Register
as the address. Timing diagrams showing the operation of the control logic are given in
Figure 2-2 and Figure 2-3 on page 2-7.
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Figure 2-2 Trace capture operation

ARM DDI 0275D