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2.5
Trigger delay counter
ARM DDI 0275D
The trigger delay counter, TrgDelayCounter, controls how many data words are
written into the trace RAM after a trigger event. When a trigger event is detected, the
Triggered flag is asserted. This enables the trigger delay counter which decrements
every time a data word is written into the trace RAM. When TrgDelayCounter reaches
zero the acquisition complete flag, AcqComp, is asserted. This prevents further writes
to the trace RAM. The AcqComp flag is cleared when trace capture is disabled
(TraceCaptEn=0). The state of the triggered flag can be read from the Status Register.
The Triggered flag is cleared when trace capture is disabled.
AcqComp is output as a signal from the macrocell for possible use by ASIC logic.
Copyright © 2002, 2003 ARM Limited. All rights reserved.
Functional Description
2-9
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