Table 3-9 Trigger Counter Register Bit Allocations; Trigger Counter Register, R7 - ARM ETB11 Technical Reference Manual

3.2.8

ARM DDI 0275D

This read/write register disables writes to the trace RAM after a defined number of

words have been stored, following the trigger event. The counter is used as follows:

Trace after The counter is set to a large value (slightly less than the number of entries

in the RAM).

Trace before The counter is set to a small value.

Trace about The counter is set to half the number of entries in the ETB11 RAM.

The register bit allocations for the Trigger Counter Register are listed in Table 3-9.

Bit number

[31: ETB_ADDR_WIDTH]

[ETB_ADDR_WIDTH-1:0]

Note

is a constant used to define the width of the trace RAM address bus.

ETB_ADDR_WIDTH

When written, the value of the Trigger Counter Register is set. You must update this

behavior.

Reading the Trigger Counter Register samples the value of the trigger counter. During

trace capture, the value of the counter can change at any time. Therefore, if a read is

performed asynchronously the returned value might be unreliable.

You cannot write to this register if TraceCaptEn is HIGH.

Table 3-9 Trigger Counter Register bit allocations

Function

Reserved.

Trigger count.

The number of datawords written into the trace RAM

following the trigger event is given by the equation:

Count = Trigger Counter Register value + 1 If this is set to

0, the trigger is ignored.

Programmer's Model

3-9

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