ARM ETB11 Technical Reference Manual page 43

Functional Description
When CReq goes HIGH, the data is already valid on HWriteData (the registered
version of HWDATA), and the address is already valid on HADDRReg. The CS,WE,
and RegWrite signals that control write access of the ETB11 RAM and the ETB11
registers then go HIGH for one cycle after CReq goes HIGH to perform the write
access. CAck then goes HIGH one cycle after CReq goes HIGH to indicate that the
write data has been used in the CLK domain.
At the same time that HAck goes HIGH, HREADYMEM goes HIGH indicating to the
AHB bus master that the data has been written to its destination.
HReq then goes LOW, indicating that the AHB transfer has finished. This, in turn,
causes CAck to go LOW one cycle after CReq goes LOW.
Finally, HAck goes LOW, finishing the write cycle.
A software write cycle with CLK and HCLK asynchronous is shown in Figure 2-11 on
page 2-24.
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