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Glossary
Clock gating
Data Abort
Debugger
Embedded Trace Macrocell (ETM)
ETM
Halfword
JTAG
Joint Test Action Group (JTAG)
Macrocell
Reserved
TAP
Test Access Port (TAP)
TPA
Glossary-2
Gating a clock signal for a macrocell with a control signal, and using the modified clock
that results to control the operating state of the macrocell.
An indication from a memory system to a core that it must halt execution of an
attempted illegal memory access. A Data Abort is attempting to access invalid data
memory.
A debugging system that includes a program, used to detect, locate, and correct software
faults, together with custom hardware that supports software debugging.
An application that monitors and controls the operation of a second application. Usually
used to find errors in the application program flow
A hardware macrocell which, when connected to a processor core, outputs instruction
and data trace information on a trace port.
See Embedded Trace Macrocell
A 16-bit data item.
See Joint Test Action Group
The name of the organization that developed standard IEEE 1149.1. This standard
defines a boundary-scan architecture used for in-circuit testing of integrated circuit
devices. It is commonly known by the initials JTAG.
A complex logic block with a defined interface and behavior. A typical VLSI system
comprises several macrocells (such as an ETM9 and a memory block) plus
application-specific logic.
A field in a control register or instruction format is reserved if the field is to be defined
by the implementation, or produces Unpredictable results if the contents of the field are
set as specified. These fields are reserved for use in future extensions of the architecture
or are implementation-specific. All reserved bits not used by the implementation must
be written as zero and will be read as zero.
See Test Access Port
The collection of four mandatory and one optional terminals that form the input and
output and control interface to a JTAG boundary-scan architecture. The mandatory
terminals are DBGTDI, DBGTDO, DBGTMS, and DBGTCK. The optional terminal
is nDBGTRST.
See Trace Port Analyzer.
Copyright © 2002, 2003 ARM Limited. All rights reserved.
ARM DDI 0275D
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