Understanding The Phase-Lock Loop Technique; The Phase Lock Loop Circuit - Agilent Technologies E5500A User Manual

Phase noise measurement system
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Understanding the
Phase-Lock Loop
Technique
Figure 6-1 Simplified Block Diagram of the Phase Lock Loop Configuration
The Phase Lock Loop
Circuit
This measurement technique requires two signal sources set up in a phase
locked loop (PLL) configuration. One of the sources is the unit-under-test
(UUT). The second source serves as the reference against which the UUT is
measured. (One of the two sources must be a VCO source capable of being
frequency tuned by the System.)
diagram of the PLL configuration used for the measurement.
The Capture and Drift Tracking Ranges
Like other PLL circuits, the phase lock loop created for the measurement has
a Capture Range and a drift tracking range. The Capture Range is equal to
5% of the system's peak tuning range, and the drift tracking range is equal to
24% of the system's peak tuning range.
The system's peak tuning range is derived from the tuning characteristics of
the VCO source you are using for the measurement.
illustrates the relationship that typically exists between the VCO's
peak-to-peak tuning range and the tuning range of the system.
The system's drift tracking range is limited to a small portion of the peak
tuning range to minimize the possibility of measurement accuracy
degradation caused by non-linearity across the VCO's tuning range.
Peak Tune Range (PTR)
PTR is determined using two parameters:
VCO tuning sensitivity (Hz/Volt)
Total voltage tuning range (Volts)
PTR = (VCO Tuning Sensitivity) X (Total Voltage Tuning Range)
PTR = (100 Hz/V) X (10 V) = 1000 Hz
Agilent Technologies E5500 Phase Noise Measurement System 6-3
Absolute Measurement Fundamentals
The Phase Lock Loop Technique
Figure 6-1 on page 6-3
shows a simplified
Figure 6-2 on page 6-4

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