EasyDrive CV3100 Series Instruction Manual page 102

CV3100 series and MINI series high performance general purpose inverter instruction manual
17: Timing to reach output
One pulse signal of 500mS width will be output when timing cumulative reach PA.07
setting.
Note: Terminal DO1，DO2 effective signals are of low voltage, asking for 24VDC
power supply connected with resistor; The relay output is digital (on-off) signal.
P4.10 FDT level setting
Setting range
P4.11 FDT lag value
Setting range
These parameters are used for setting frequency checkout level. When frequency
output rise exceeds FDT level setting, inverter has open-loop collector output; when
the frequency output decrease to the value less FDT lag value, inverter has high
resistance status output, shown as Diagram 6-16:
P4.12 Freq. arrival FAR checkout width
Setting range
When output frequency of inverter is in the range of positive/negative checkout of
setting frequency, the selected output terminals will output open collector signal.
shown as Diagram 6-17:
0.00Hz—upper limit frequency
0.00Hz—30.00Hz
FDT level
Doi
Diagram 6-16 FDT setting
0.00—15.00Hz
Factory setting
Factory setting
FDT Lag value
time
time
Factory setting
6-34
0.00Hz
1.00Hz
0.00Hz