Baud Rate Setting; Notes On Use Of Fifos - Renesas EMMA Mobile 1 User Manual

5.2 Baud Rate Setting

A baud rate is determined according to the settings for serial clock input and the DLM and DLL registers. EM1
assumes that the serial clocks below are input.
Clock frequencies can be set individually. For details about clock settings, see the Multimedia Processor for
Mobile Applications - System Control/General-Purpose I/O Interface User's Manual (S19265E).
Clock [Hz] Clock Source
Frequency
229.376 M PLL3
Clock [Hz] Clock Source
Frequency
7.168 M PLL3/32

5.3 Notes on Use of FIFOs

UART and the internal bus communicate via a 2-byte interface, so the FIFOs can be read or written at the same
time in 2-byte units, but note the following:
(1) An overrun error occurs when 2-byte data is written in response to a DMA request when only 1 byte of space is
available in the transmit FIFO in the DMA mode 1.
(2) When a reception timeout event occurs in DMA mode 1 while the timeout interrupt is enabled (bit 4 of the IER
register = 0), the host cannot determine whether the request is issued due to a timeout event or the trigger
level. As a result, if 2 bytes are read in response to a DMA request, a FIFO underrun error occurs.
46
CHAPTER 5 USAGE
Baud Rate Error DLMR
(bps) Range
2400 ±4 23
4800 11
9600 5
19200 2
38400 1
57600 0
115200 0
Baud Rate Error DLMR
(bps) Range
2400 ±4 0
4800 0
9600 0
19200 0
38400 0
57600 0
115200 0
User's Manual S19262EJ3V0UM
DLLR Actual Baud Error
Rate (bps) (%)
85 2400.13394 0.0055807
0.011159
171 4799.46435
213 9602.14334 0.0223264
0.044623
235 19191.4324
117 38434.3164 0.0893655
0.044623
249 57574.2972
124 115612.903 0.3584229
DLLR Actual Baud Error
Rate (bps) (%)
0.178253
187 2395.72193
93 4817.2043 0.3584229
0.70922
47 9531.91489
23 19478.2609 1.4492754
2.777778
12 37333.3333
2.777778
8 56000
2.777778
4 112000