Hardware Control Register - Renesas EMMA Mobile 1 User Manual

3.2.12 Hardware control register

This additional register (HCR0: 5000_002CH (UART0), 5001_002CH (UART1), 5002_002CH (UART2)) controls
the DMA controller and other hardware.
15 14
7 6
SW Reset RTS Mode
Name R/W
Reserved R
SW Reset R/W
RTS Mode R/W
DMA 2Byte Access R/W
Enable
Receiver timeout DMA R/W
Disable
Receiver DMA Mode R/W
Transmitter DMA Mode R/W
Receiver DMA Enable R/W
Transmitter DMA R/W
Enable
30
CHAPTER 3 REGISTERS
13 12
Reserved
5 4
DMA 2Byte Receiver
Access Enable timeout DMA
Disable
Bit After Reset
15:8 0 Reserved. When these bits are read, 0 is returned for each bit.
7 0 Setting this bit to 1 resets internal UART registers, except for
registers for the transmit and receive FIFOs and baud rate generator
(RBR/THR, DLL, and DLM). Setting this bit to 0 cancels the reset.
Caution Before executing a software reset, reset the transmit
6 0 Selects the RTS mode when auto-RTS is used.
0: Auto-RTS mode 0
1: Auto-RTS mode 1
5 0 Selects the width of data to transfer to the transmit and receive
FIFOs via DMA.
0: 1 byte
1: 2 bytes
This setting affects the conditions for generating DMA request
signals.
4 0 Specifies whether to include the timeout event in the reception DMA
transfer request sources.
0: Includes the timeout event in the reception DMA transfer request
sources.
1: Excludes the timeout event from the reception DMA transfer
request sources (and automatically adds it to the interrupt
sources).
3 0 Specifies the DMA request mode separately for transmission and
reception. These bits are used with bit 3 of the FCR register.
2 0
1 0 Specifies whether to enable the reception DMA request output.
0: Disables reception DMA requests.
1: Enables reception DMA requests.
0 0 Specifies whether to enable the transmission DMA request output.
0: Disables transmission DMA requests.
1: Enables transmission DMA requests.
User's Manual S19262EJ3V0UM
11 10
3 2
Receiver DMA Transmitter
Mode DMA Mode
Function
and receive FIFOs (bits 2 and 1 of FCR register). After
that, registers other than the DLL and DLM registers
must be set up again.
9 8
1 0
Receiver DMA Transmitter
Enable DMA Enable