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3.3.3 IR control register 2
This register (IRCR2: 5000_0048H (UART0), 5001_0048H (UART1), 5002_0048H (UART2)) specifies the receive
data mask period to add at the end of IR transmission.
The IRCR2, IRCR3, and IRCR4 register bits (MASK_PERIOD[19:0], 20 bits in total) are used for specification.
15
14
7
6
Name
Reserved
MASK_PERIOD[7:0]
3.3.4 IR control register 3
This register (IRCR3: 5000_004CH (UART0), 5001_004CH (UART1), 5002_004CH (UART2)) specifies the receive
data mask period to add at the end of IR transmission.
The IRCR2, IRCR3, and IRCR4 register bits (MASK_PERIOD[19:0], 20 bits in total) are used for specification.
15
14
7
6
Name
Reserved
MASK_PERIOD[15:8]
CHAPTER 3 REGISTERS
13
12
5
4
MASK_PERIOD[7:0]
R/W
Bit
After Reset
R
15:8
0
R/W
7:0
00H
13
12
5
4
MASK_PERIOD[15:8]
R/W
Bit
After Reset
R
15:8
0
R/W
7:0
00H
User's Manual S19262EJ3V0UM
11
10
Reserved
3
2
Function
Reserved. When these bits are read, 0 is returned for each bit.
Specifies the receive data mask period to add at the end of IR
transmission. The lower 8 bits are specified.
11
10
Reserved
3
2
Function
Reserved. When these bits are read, 0 is returned for each bit.
Specifies the receive data mask period to add at the end of IR
transmission. The middle 8 bits are specified.
9
8
1
0
9
8
1
0
35
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