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3.3.2 IR control register 1
This register (IRCR1: 5000_0044H (UART0), 5001_0044H (UART1), 5002_0044H (UART2)) specifies the valid
reception pulse width.
15
14
7
6
Name
R/W
Reserved
R
PULSE_WIDTH[7:0]
R/W
Cautions 1. The valid reception pulse width is expressed by using the following expression:
Valid reception pulse width (
2. Valid reception pulses are detected by sampling reception pulses based on the XIN clock
cycles.
successively detected the number of times specified for this register, the pulse is modulated
as a valid pulse.
Depending on the phase of the reception pulse and XIN clock, a pulse that does not satisfy
the above expression might be modulated as a valid pulse.
condition under which the reception pulse is always judged to be invalid:
Invalid reception pulse width (
Example
When the PULSE_WIDTH field is set to 02H
<1>
Valid reception pulse width (
<2>
Invalid reception pulse width (
34
CHAPTER 3 REGISTERS
13
12
5
4
PULSE_WIDTH[7:0]
Bit
After Reset
15:8
0
7:0
02H
s) (PULSE_WIDTH[7:0] + 1) 1/f
When the pulse level (specified by the IR_RXPSEL bit of the IRCR0 register) is
s) < Approx. (PULSE_WIDTH[7:0] 1) 1/f
s) 3 1/f
s) < 1 1/f
Reception pulse
XIN
User's Manual S19262EJ3V0UM
11
10
Reserved
3
2
Reserved. When these bits are read, 0 is returned for each bit.
Specifies the valid reception pulse width.
Valid width: "Value set to this bit + 1" × 1 / f
Settable range: 02H to FFH (The settings 00H and 01H are
prohibited.)
(MHz)
XIN
(MHz)
XIN
<1>
<2>
9
1
Function
or longer
XIN
(MHz)
XIN
The following shows the
(MHz)
XIN
8
0
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