Renesas EMMA Mobile 1 User Manual
  1. Manuals
  2. Brands
  3. Renesas Manuals
  4. Computer Hardware
  5. EMMA Mobile 1
  6. User manual
Renesas EMMA Mobile 1 User Manual

Renesas EMMA Mobile 1 User Manual

Multimedia processor for mobile applications uart interface
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
To our customers,
st
On April 1
, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Old Company Name in Catalogs and Other Documents
Renesas Electronics website: http://www.renesas.com
st
April 1
, 2010
Renesas Electronics Corporation

Advertisement

Table of Contents
loading

Related Manuals for Renesas EMMA Mobile 1

Summary of Contents for Renesas EMMA Mobile 1

  • Page 1 On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding.
  • Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
  • Page 3 User’s Manual Multimedia Processor for Mobile Applications UART Interface EMMA Mobile Document No. S19262EJ3V0UM00 (3rd edition) Date Published September 2009 2009 Printed in Japan...
  • Page 4 [MEMO] User’s Manual S19262EJ3V0UM...
  • Page 5 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
  • Page 6 The names of other companies and products are the registered trademarks or trademarks of the respective company. • The information in this document is current as of September, 2009. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets, etc., for the most up-to-date specifications of NEC Electronics products.
  • Page 7 PREFACE Readers This manual is intended for hardware/software application system designers who wish to understand and use the UART interface functions of EMMA Mobile1 (EM1), a multimedia processor for mobile applications. Purpose This manual is intended to explain to users the hardware and software functions of the UART interface of EM1, and be used as a reference material for developing hardware and software for systems that use EM1.
  • Page 8 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Document Name Document No. MC-10118A Data sheet S19657E μPD77630A Data sheet S19686E User’s manual Audio/Voice and PWM Interfaces S19253E DDR SDRAM Interface S19254E DMA Controller...

  • Page 9: Table Of Contents

    CONTENTS CHAPTER 1 OVERVIEW..........................10 Function Overview ........................10 Features .............................10 I/O Signals..........................10 CHAPTER 2 PIN FUNCTIONS ........................11 UART Interface Pins .........................11 CHAPTER 3 REGISTERS ........................12 Registers............................12 UART Registers.........................13 3.2.1 Receive buffer/transmit hold register .................... 13 3.2.2 Interrupt enable register ........................ 15 3.2.3 Interrupt identification register.......................
  • Page 10 IR Encoder/Decoder Functions....................41 4.6.1 Transmission data modulation by IR encoder ................42 4.6.2 Reception data demodulation by IR decoder ................42 4.6.3 Masking of reception data for IR decoder echo cancellation ............43 4.6.4 Cautions on using IR encoder/decoder ..................44 CHAPTER 5 USAGE..........................45 Initialization Method........................45 5.1.1 Initialization ...........................45...
  • Page 11 LIST OF FIGURES Figure No. Title Page Figure 4-1. IR Encoder/Decoder Block Diagram ......................41 Figure 4-2. Transmission Data Modulation Example ....................42 Figure 4-3. Reception Data Demodulation Example ....................42 Figure 4-4. IrPHY Ver. 1.4 Block Configuration Example.....................44 LIST OF TABLES Table No. Title Page Table 3-1.

  • Page 12: Chapter 1 Overview

    CHAPTER 1 OVERVIEW This chapter describes the Universal Asynchronous Receiver/Transmitter (UART) for EM1. 1.1 Function Overview The UART block incorporated in EM1 has two 64-byte FIFO buffers, one for transmission and one for reception, and is compatible with TL16C750, a general-purpose UART chip. The IrDA SIR encoder/decoder is provided for the serial interface, which enables transmission and reception by using the RZI (Return-to-Zero-Inverted) signal.

  • Page 13: Chapter 2 Pin Functions

    CHAPTER 2 PIN FUNCTIONS 2.1 UART Interface Pins Pin Name After Reset Function Alternate Pin Function   URT0_SRIN Input Serial data  URT0_SOUT Output Serial data  URT0_CTSB Input Prepared to transmit or receive connected GIO_P85 device data URT1_SRIN URT0_RTSB Output Prepared to transmit or receive data...

  • Page 14: Chapter 3 Registers

    CHAPTER 3 REGISTERS UART register addresses use half-word boundaries. 3.1 Registers The offset addresses 0000H to 0034H are assigned to UART registers, and 0040H to 0050H are assigned to IR encoder/decoder registers. Do not access reserved registers. The value 0000_0000H is returned for a read access. Do not write any value other than 0 to the reserved bits in each register.

  • Page 15: Uart Registers

    CHAPTER 3 REGISTERS 3.2 UART Registers 3.2.1 Receive buffer/transmit hold register This register (RBR/THR: 5000_0000H (UART0), 5001_0000H (UART1), 5002_0000H (UART2)) is used to read received data and write data to transmit. This register functions as the receive buffer register (RBR) when read, or as the transmit hold register (THR) when written.
  • Page 16 CHAPTER 3 REGISTERS Cautions 1. If data is written to the transmit FIFO when it is full or if 2-byte data is written to the transmit FIFO when only 1 byte of space is available, an overrun error occurs and no data is written to the transmit FIFO.

  • Page 17: Interrupt Enable Register

    CHAPTER 3 REGISTERS 3.2.2 Interrupt enable register This register (IER: 5000_0004H (UART0), 5001_0004H (UART1), 5002_0004H (UART2)) enables the issuance of interrupt requests. Each interrupt can be set up individually for each interrupt source. The interrupt sources corresponding to bits to which 1 is written are enabled. Reserved Reserved EDSSI...

  • Page 18: Interrupt Identification Register

    CHAPTER 3 REGISTERS 3.2.3 Interrupt identification register This register (IIR: 5000_0008H (UART0), 5001_0008H (UART1), 5002_0008H (UART2)) is used to identify interrupt sources. The FIFO operating mode and interrupt sources can be checked by reading this register. When multiple interrupts sources are generated, the interrupt source that has the highest priority is output to this register.

  • Page 19: Table 3-2. Interrupt Indication And Prioritization Of Interrupt Sources (Bits 3 To 0 Of Iir)

    CHAPTER 3 REGISTERS Table 3-2. Interrupt Indication and Prioritization of Interrupt Sources (Bits 3 to 0 of IIR) IIR[3:0] Priority Interrupt Type Interrupt Source Interrupt Reset Method 0001 (1h) None None None None 0110 (6h) Reception error When at least one of the following When the line status register (receiver line status) occurs:...

  • Page 20: Fifo Control Register

    CHAPTER 3 REGISTERS 3.2.4 FIFO control register This register (FCR: 5000_000CH (UART0), 5001_000CH (UART1), 5002_000CH (UART2)) controls the transmit/receive FIFO. Reserved Receiver Trigger 64 Byte FIFO Reserved DMA Mode Transmitter Receiver FIFO FIFO Enable Enabled Select FIFO Reset Reset Name After Reset Function Reserved...

  • Page 21: Table 3-3. Reception Trigger Level Settings (Bits 7 And 6 Of Fcr)

    CHAPTER 3 REGISTERS * If a register value is changed during operation, normal operation is not guaranteed. In this case, initialize the register. Table 3-3. Reception Trigger Level Settings (Bits 7 and 6 of FCR) 16-byte FIFO Mode 64-byte FIFO Mode Bits 7 to 6 of (Bit 5 of FCR Register = 0) (Bit 5 of FCR Register = 1)
  • Page 22 CHAPTER 3 REGISTERS Notes 1. The timeout event can be excluded from the reception DMA request issue conditions by setting bit 4 of the HCR0 register. Bit 4 = 0: The timeout event is included in the reception DMA request issue conditions. Bit 4 = 1: The timeout event is excluded from the reception DMA request issue conditions and added to the interrupt sources.

  • Page 23: Line Control Register

    CHAPTER 3 REGISTERS 3.2.5 Line control register This register (LCR: 5000_0010H (UART0), 5001_0010H (UART1), 5002_0010H (UART2)) specifies the transmission/reception data format and enables access to the divisor latch. Reserved DLAB Break Control Stick Parity WLS[1:0] (1/2) Name After Reset Function Reserved 15:8 Reserved.

  • Page 24: Table 3-6. Parity Type Settings (Bits 5 To 3 Of Lcr)

    CHAPTER 3 REGISTERS (2/2) Name After Reset Function STB * Specifies the number of stop bits to add to data transferred via serial transmission. 0: 1 bit 1: 2 bits Only the first stop bit is checked on the reception side, regardless of this setting.

  • Page 25: Modem Control Register

    CHAPTER 3 REGISTERS 3.2.6 Modem control register This register (MCR: 5000_0014H (UART0), 5001_0014H (UART1), 5002_0014H (UART2)) controls the interface with modems (and other peripheral devices). Reserved Reserved Reserved OUT2 OUT1 Name After Reset Function Reserved 15:8 Reserved. When these bits are read, 0 is returned for each bit. Reserved Reserved.

  • Page 26: Table 3-8. Auto-Flow Settings (Bits 5 And 1 Of Mcr And Bit 6 Of Hcr0)

    CHAPTER 3 REGISTERS Table 3-8. Auto-Flow Settings (Bits 5 and 1 of MCR and Bit 6 of HCR0) Bit 5 of MCR Bit 1 of MCR Bit 6 of HCR0 Auto-CTS Auto-RTS Register Register Register   (Auto-RTS mode 0) ...

  • Page 27: Line Status Register

    CHAPTER 3 REGISTERS 3.2.7 Line status register This register (LSR: 5000_0018H (UART0), 5001_0018H (UART1), 5002_0018H (UART2)) is used to check the status of transmission and reception. Reserved Error in TEMT THRE Receiver FIFO (1/2) Name After Reset Function Reserved 15:8 Reserved.
  • Page 28 CHAPTER 3 REGISTERS (2/2) Name After Reset Function FE * This bit is set to “1” when a framing error is detected in received data. Reading this register clears this bit to “0”. A framing error occurs when the first stop bit following the data bit or parity bit of received data is checked and it is judged to be invalid (low level).

  • Page 29: Modem Status Register

    CHAPTER 3 REGISTERS 3.2.8 Modem status register This register (MSR: 5000_001CH (UART0), 5001_001CH (UART1), 5002_001CH (UART2)) is used to check the control signals connected to modems (or other peripheral devices). Reserved    TERI Name After Reset Function Reserved 15:8 Reserved.

  • Page 30: Scratch Register

    CHAPTER 3 REGISTERS 3.2.9 Scratch register This register (SCR: 5000_0020H (UART0), 5001_0020H (UART1), 5002_0020H (UART2)) can be used freely during programming. Reserved Scratch Register Name After Reset Function Reserved 15:8 Reserved. When these bits are read, 0 is returned for each bit. Scratch Register These bits do not affect the UART operation and can be used freely during programming.

  • Page 31: Divisor Latch Ms Byte Register

    CHAPTER 3 REGISTERS 3.2.11 Divisor latch MS byte register This register (DLM: 5000_0028H (UART0), 5001_0028H (UART1), 5002_0028H (UART2)) specifies the higher 8 bits of the divisor for the baud rate generator. Set up this register in combination with the DLL register that specifies the lower 8 bits.

  • Page 32: Hardware Control Register

    CHAPTER 3 REGISTERS 3.2.12 Hardware control register This additional register (HCR0: 5000_002CH (UART0), 5001_002CH (UART1), 5002_002CH (UART2)) controls the DMA controller and other hardware. Reserved SW Reset RTS Mode DMA 2Byte Receiver Receiver DMA Transmitter Receiver DMA Transmitter Access Enable timeout DMA Mode DMA Mode...

  • Page 33: Hardware Status Register 2

    CHAPTER 3 REGISTERS 3.2.13 Hardware status register 2 This additional register (HCR2: 5000_0030H (UART0), 5001_0030H (UART1), 5002_0030H (UART2)) is used to check the receive FIFO status. Reserved Receiver FIFO Receiver FIFO Data Count[6:0] Underrun Name After Reset Function Reserved 15:8 Reserved.

  • Page 34: Hardware Status Register 3

    CHAPTER 3 REGISTERS 3.2.14 Hardware status register 3 This additional register (HCR3: 5000_0034H (UART0), 5001_0034H (UART1), 5002_0034H (UART2)) is used to check the transmit FIFO status. Reserved Transmitter Transmitter FIFO Data Count[6:0] FIFO Overrun Name After Reset Function Reserved 15:8 Reserved.

  • Page 35: Ir Encoder/Decoder Registers

    CHAPTER 3 REGISTERS 3.3 IR Encoder/Decoder Registers 3.3.1 IR control register 0 This register (IRCR0: 5000_0040H (UART0), 5001_0040H (UART1), 5002_0040H (UART2)) controls the IrDA SIR (2.4 to 115.2 kbps) encoder/decoder. Reserved Reserved IR_MASK_ IR_RXPSEL IR_RXEN Reserved IR_TXPSEL IR_MODE Name After Reset Function Reserved 15:8...

  • Page 36: Ir Control Register 1

    CHAPTER 3 REGISTERS 3.3.2 IR control register 1 This register (IRCR1: 5000_0044H (UART0), 5001_0044H (UART1), 5002_0044H (UART2)) specifies the valid reception pulse width. Reserved PULSE_WIDTH[7:0] Name After Reset Function Reserved 15:8 Reserved. When these bits are read, 0 is returned for each bit. PULSE_WIDTH[7:0] Specifies the valid reception pulse width.

  • Page 37: Ir Control Register 2

    CHAPTER 3 REGISTERS 3.3.3 IR control register 2 This register (IRCR2: 5000_0048H (UART0), 5001_0048H (UART1), 5002_0048H (UART2)) specifies the receive data mask period to add at the end of IR transmission. The IRCR2, IRCR3, and IRCR4 register bits (MASK_PERIOD[19:0], 20 bits in total) are used for specification. Reserved MASK_PERIOD[7:0] Name...

  • Page 38: Ir Control Register 4

    CHAPTER 3 REGISTERS 3.3.5 IR control register 4 This register (IRCR4: 5000_0050H (UART0), 5001_0050H (UART1), 5002_0050H (UART2)) specifies the receive data mask period to add at the end of IR transmission. The IRCR2, IRCR3, and IRCR4 register bits (MASK_PERIOD[19:0], 20 bits in total) are used for specification. Reserved Reserved MASK_PERIOD[19:16]...

  • Page 39: Chapter 4 Description Of Functions

    CHAPTER 4 DESCRIPTION OF FUNCTIONS 4.1 Auto-Flow Mode In auto-flow mode, the connected devices are also assumed to operate in auto-flow mode. If a connected device does not stop transmission by pulling RTSZ high, an overrun error occurs. (1) HCR0 software reset Almost all UART interface registers are initialized by setting bit 7 of the HCR0 register to 1, except for the FIFOs.

  • Page 40: Fifos

    CHAPTER 4 DESCRIPTION OF FUNCTIONS 4.2 FIFOs 4.2.1 Operation in FIFO interrupt mode The following interrupts occur while the receive FIFO interrupt is enabled (when bit 0 of the FCR register, bit 0 of the IER register, and bit 2 of the IER register are set to 1). ...

  • Page 41: Interrupt Sources

    CHAPTER 4 DESCRIPTION OF FUNCTIONS 4.3 Interrupt Sources The UART interface uses four interrupts. Table 4-1. Interrupt Sources Interrupt Name Bit Assignment Modem status interrupt Bit 3 (EDSSI) of the IER register Reception error (receiver line status) interrupt Bit 2 (ELSI) of the IER register Transmit buffer empty (transmit hold register (THR) empty) Bit 1 (ETBEI) of the IER register interrupt...

  • Page 42: Timing Of Auto-Flow Cts Control

    CHAPTER 4 DESCRIPTION OF FUNCTIONS 4.5.2 Timing of auto-flow CTS control 4.5.3 Timing of auto-flow RTS control User’s Manual S19262EJ3V0UM...

  • Page 43: Ir Encoder/Decoder Functions

    CHAPTER 4 DESCRIPTION OF FUNCTIONS 4.6 IR Encoder/Decoder Functions EM1 incorporates an IrDA SIR (2.4 to 115.2 kbps) encoder/decoder (IR encoder/decoder). Figure 4-1 shows a block diagram of the IR encoder/decoder. The IR transmission/reception mode is entered when bit 0 (IR_MODE) of the IRCR0 register is set to 1. (The IR encoder/decoder is inserted into the data path used for transmission and reception via the UARTx_SIN and UARTx_SOUT pins.) Figure 4-1.

  • Page 44: Transmission Data Modulation By Ir Encoder

    CHAPTER 4 DESCRIPTION OF FUNCTIONS 4.6.1 Transmission data modulation by IR encoder When the transmitted data value is 0, a pulse with the width of the baud rate cycle multiplied by 3/16 is output. The polarity of transmission pulses can be selected by using bit 1 (IR_TXPSEL) of the IRCR0 register. Figure 4-2.

  • Page 45: Masking Of Reception Data For Ir Decoder Echo Cancellation

    CHAPTER 4 DESCRIPTION OF FUNCTIONS Table 4-2. PULSE_WIDTH[7:0] Setting Examples Desired Valid = 1.8432 MHz = 3.072 MHz = 14.7456 MHz = 50 MHz Reception PULSE_ Measured PULSE_ Measured PULSE_ Measured PULSE_ Measured Pulse Width WIDTH[7:0] Valid WIDTH[7:0] Valid WIDTH[7:0] Valid WIDTH[7:0] Valid...

  • Page 46: Cautions On Using Ir Encoder/Decoder

    CHAPTER 4 DESCRIPTION OF FUNCTIONS 4.6.4 Cautions on using IR encoder/decoder (1) Cautions on changing the IR control register settings Be sure to set bit 4 (IR_RXEN) of the IRCR0 register to 0 (to stop reception) before changing the register settings that specify the reception by the IR decoder.

  • Page 47: Chapter 5 Usage

    CHAPTER 5 USAGE 5.1 Initialization Method 5.1.1 Initialization This section describes initial settings necessary for operating the UART interface. (1) Baud rate settings and enabling 64-byte FIFO mode Set bit 7 (DLAB) of the LCR register to 1 and specify a baud rate in the DLM and DLL registers. After the above settings, LCR [7] is to set it in = 0, and generation of 16x clock is begun.

  • Page 48: Baud Rate Setting

    CHAPTER 5 USAGE 5.2 Baud Rate Setting A baud rate is determined according to the settings for serial clock input and the DLM and DLL registers. EM1 assumes that the serial clocks below are input. Clock frequencies can be set individually. For details about clock settings, see the Multimedia Processor for Mobile Applications - System Control/General-Purpose I/O Interface User's Manual (S19265E).
  • Page 49 Revision History Date Revision Comments February 10, 2009 − April 27, 2009 Incremental update from comments to the 1.0.. September 30, 2009 Incremental update from comments to the 2.0.. User’s Manual S19262EJ3V0UM...
  • Page 50 For further information, please contact: NEC Electronics Corporation 1753, Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [Asia & Oceania] [America] [Europe] NEC Electronics (China) Co., Ltd NEC Electronics America, Inc. NEC Electronics (Europe) GmbH 7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian 2880 Scott Blvd.

Table of Contents