Ir Control Register 4 - Renesas EMMA Mobile 1 User Manual

3.3.5 IR control register 4

This register (IRCR4: 5000_0050H (UART0), 5001_0050H (UART1), 5002_0050H (UART2)) specifies the receive
data mask period to add at the end of IR transmission.
The IRCR2, IRCR3, and IRCR4 register bits (MASK_PERIOD[19:0], 20 bits in total) are used for specification.
15 14
7 6
Reserved
Name
Reserved
MASK_PERIOD[19:16]
Caution The mask extension period is expressed by using the following equation:
Mask extension period [
Bit time
Transmit data
UARTx_SOUT
(IR_TXPSEL = 0)
Receive data
masking
36
CHAPTER 3 REGISTERS
13 12
5 4
R/W Bit After Reset
R 15:4 0
R/W 3:0 00H

s) = (MASK_PERIOD[19:0] + 2)  1/f
Start
0 1 0 1
User's Manual S19262EJ3V0UM
11 10
Reserved
3 2
MASK_PERIOD[19:16]
Function
Reserved. When these bits are read, 0 is returned for each bit.
Specifies the receive data mask period to add at the end of IR
transmission. The higher 4 bits are specified.
XIN
0 0 1 1
9 8
1 0
(MHz)
Stop
0 1
Mask extension
period