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Cautions 1. If data is written to the transmit FIFO when it is full or if 2-byte data is written to the transmit
FIFO when only 1 byte of space is available, an overrun error occurs and no data is written to
the transmit FIFO. When an overrun error occurs, bit 7 of the HCR3 register is set to 1.
2. When data is read from the empty receive FIFO or if the reading of 2-byte data from the
receive FIFO is attempted when only 1 byte of data is stored, an underrun error occurs and
data is not read from the receive FIFO. (All zeros are output to the host bus interface.) When
an underrun error occurs, bit 7 of the HCR2 register is set to 1.
3. If the number of transmitted or received data bits is 5 to 7 bits, data in the lower bits is
transmitted or received and bits exceeding the specified transfer bit count are discarded.
Example
14
CHAPTER 3 REGISTERS
When the transfer bit count is set to 5 (bits 1 and 0 (WLS) of LCR register = 00b):
On the transmission side, data of bits 7 to 5 is discarded and data of bits 4 to 0 is
transmitted.
On the reception side, "0" is written to bits 7 to 5 and valid data is written to bits 4 to 0.
User's Manual S19262EJ3V0UM
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