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3.2.13 Hardware status register 2
This additional register (HCR2: 5000_0030H (UART0), 5001_0030H (UART1), 5002_0030H (UART2)) is used to
check the receive FIFO status.
15
14
7
6
Receiver FIFO
Underrun
Name
Reserved
Receiver FIFO Underrun
Receiver FIFO Data
Count[6:0]
CHAPTER 3 REGISTERS
13
12
Reserved
5
4
Receiver FIFO Data Count[6:0]
R/W
Bit
After Reset
R
15:8
0
R
7
0
R
6:0
0
User's Manual S19262EJ3V0UM
11
10
3
2
Reserved. When these bits are read, 0 is returned for each bit.
When data is read from the receive FIFO when it is empty or when
reading of 2-byte data from the receive FIFO is attempted when only
1 byte is stored, an underrun error occurs and this bit is set to 1.
Reading this register clears this bit to "0".
Caution If an underrun error occurs, the receive FIFO is no
longer read and all zeros are output to the host bus
interface. No interrupt request is caused by an
underrun error.
Indicates the number of data items remaining in the receive FIFO.
9
1
Function
8
0
31
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