Table of Contents
Advertisement
3.3 IR Encoder/Decoder Registers
3.3.1 IR control register 0
This register (IRCR0: 5000_0040H (UART0), 5001_0040H (UART1), 5002_0040H (UART2)) controls the IrDA SIR
(2.4 to 115.2 kbps) encoder/decoder.
15
14
7
6
Reserved
IR_MASK_
OFF
Name
R/W
Reserved
R
Reserved
R/W
IR_MASK_OFF
R/W
IR_RXPSEL
R/W
IR_RXEN
R/W
Reserved
R/W
IR_TXPSEL
R/W
IR_MODE
R/W
CHAPTER 3 REGISTERS
13
12
Reserved
5
4
IR_RXPSEL
IR_RXEN
Bit
After Reset
15:8
0
Reserved. When these bits are read, 0 is returned for each bit.
7
0
Reserved. Written data is ignored.
6
0
Specifies whether to enable masking of received data (stopping
pulse detection) for echo cancellation.
0: Enables masking of received data.
1: Disables masking of received data.
5
0
Specifies the polarity of reception pulses.
0: Low
1: High
4
0
Specifies whether to enable reception.
0: Stops reception.
1: Enables reception
3:2
0
Reserved. Written data is ignored.
1
0
Specifies the polarity of transmission pulses.
0: Low
1: High
0
0
Specifies the operating mode.
0: UART mode
1: IR transmission/reception mode
User's Manual S19262EJ3V0UM
11
10
3
2
Reserved
IR_TXPSEL
Function
9
8
1
0
IR_MODE
33
Advertisement
Table of Contents
