Table of Contents
Advertisement
Notes 1. The timeout event can be excluded from the reception DMA request issue conditions by setting bit 4 of
the HCR0 register.
Bit 4 = 0: The timeout event is included in the reception DMA request issue conditions.
Bit 4 = 1: The timeout event is excluded from the reception DMA request issue conditions and added
2. If an odd number of data bytes is received in the 2-byte access mode, the reception DMA request is
canceled when the amount of data remaining in the receive FIFO becomes 1 byte. When receiving an
odd number of data bytes, use 1-byte access or notify the timeout event by using an interrupt (bit 4 of
HCR0 register = 1) and read the timeout data by servicing the interrupt.
Caution In the non-FIFO mode, operation equivalent to mode 0 is performed regardless of the settings of
bit 3 in the FCR register and bits 3 and 2 in the HCR0 register.
A reception DMA request is issued when receiving 1-byte data in the receive buffer register is
completed. The request is canceled when the receive buffer register is empty.
A transmission DMA request is issued when the request transmit buffer is empty.
request is canceled when at least 1-byte data is stored in the transmit buffer.
20
CHAPTER 3 REGISTERS
to the interrupt sources.
User's Manual S19262EJ3V0UM
The
Advertisement
Table of Contents
