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3.2.11 Divisor latch MS byte register
This register (DLM: 5000_0028H (UART0), 5001_0028H (UART1), 5002_0028H (UART2)) specifies the higher 8
bits of the divisor for the baud rate generator. Set up this register in combination with the DLL register that specifies
the lower 8 bits.
The baud rate generator divides the reference clock (XIN) and generates a 16x baud rate clock for the transmit and
receive blocks by using the value specified in this register.
15
14
7
6
Name
R/W
Reserved
R
Divisor[15:8] *
R/W
* If a register value is changed during operation, normal operation is not guaranteed. In this case, initialize the
register.
Caution When the DLM and DLL registers are set up, bit 7 (DLAB) of the LCR register must be set to 1.
The DLAB bit must be set to 0 after the DLM and DLL registers are written. For details, see 3.2.5
Line control register.
CHAPTER 3 REGISTERS
13
12
Reserved
5
4
Divisor[15:8]
Bit
After Reset
15:8
0
Reserved. When these bits are read, 0 is returned for each bit.
7:0
0
Specifies the higher 8 bits of the divisor.
User's Manual S19262EJ3V0UM
11
10
3
2
Function
9
8
1
0
29
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