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3.2.14 Hardware status register 3
This additional register (HCR3: 5000_0034H (UART0), 5001_0034H (UART1), 5002_0034H (UART2)) is used to
check the transmit FIFO status.
15
14
7
6
Transmitter
FIFO Overrun
Name
Reserved
Transmitter FIFO Overrun
Transmitter FIFO Data
Count[6:0]
32
CHAPTER 3 REGISTERS
13
12
Reserved
5
4
Transmitter FIFO Data Count[6:0]
R/W
Bit
After Reset
R
15:8
0
R
7
0
R
6:0
0
User's Manual S19262EJ3V0UM
11
10
3
2
Reserved. When these bits are read, 0 is returned for each bit.
When data is written to the transmit FIFO when it is full or when 2-
byte data is written to the transmit FIFO when only 1 free byte space
is available, an overrun error occurs and this bit is set to 1.
Reading this register clears this bit to "0".
Caution If an overrun error occurs, the transmit FIFO is no
longer written. No interrupt request is caused by an
overrun error.
Indicates the number of data items remaining in the transmit FIFO.
9
1
Function
8
0
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