Page 1 REJ09B0001-0200Z R8C/Tiny Series Software Manual RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER Rev. 2.00 Revision date: Oct 17, 2005 www.renesas.com...
Page 2 Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers con- tact Renesas Technology Corp.
Page 3 Using This Manual This software manual is written for the R8C/Tiny Series. It applies to all microcomputers integrating the R8C/Tiny Series CPU core. The reader of this manual is assumed to have a basic knowledge of electrical circuits, logic circuits, and microcomputers.
Page 4 • Usage and application examples of peripheral functions • Sample programs • Introduction to the basic functions in the M16C family • Programming method with Assembly and C languages RENESAS TECHNICAL Preliminary report about the specification of a product, a document, etc. UPDATE NOTES: 1.
Page 5: Table Of Contents
Table of Contents Chapter 1 Overview ___________________________________________________ 1.1 Features of R8C/Tiny Series ...................... 2 1.1.1 Features of R8C/Tiny Series ....................2 1.1.2 Speed Performance ......................2 1.2 Address Space ........................... 3 1.3 Register Configuration ........................ 4 1.3.1 Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3) ..........4 1.3.2 Address Registers (A0 and A1) ..................
Page 6 1.8 Data Arrangement ........................16 1.8.1 Data Arrangement in Register ..................16 1.8.2 Data Arrangement in Memory ................... 17 1.9 Instruction Formats ........................18 1.9.1 Generic Format (:G) ......................18 1.9.2 Quick Format (:Q) ......................18 1.9.3 Short Format (:S) ......................18 1.9.4 Zero Format (:Z) .......................
Page 7 5.2 Interrupt Control ........................249 5.2.1 I Flag ..........................249 5.2.2 IR Bit ..........................249 5.2.3 ILVL2 to ILVL0 bis, IPL ....................250 5.2.4 Changing Interrupt Control Register ................251 5.3 Interrupt Sequence .........................252 5.3.1 Interrupt Response Time ....................253 5.3.2 Changes of IPL When Interrupt Request Acknowledged ..........253 5.3.3 Saving Register Contents ....................254 5.4 Returning from Interrupt Routines ..................255 5.5 Interrupt Priority ........................
Page 8 Quick Reference in Alphabetic Order Page No. for Page No. for Page No. for Page No. for Mnemonic Mnemonic Instruction Code Instruction Code Function Function /No. of Cycles /No. of Cycles DIVU DIVX ADCF DSBB DSUB ADJNZ ENTER EXITD BAND EXTS BCLR FCLR...
Page 9 Quick Reference in Alphabetic Order Page No. for Page No. for Page No. for Page No. for Mnemonic Mnemonic Instruction Code Instruction Code Function Function /No. of Cycles /No. of Cycles MOVHH MOVHL MOVLH SBJNZ MOVLL MULU SMOVB SMOVF SSTR STCTX POPC STNZ...
Page 10 Quick Reference by Function Page No. for Page No. for Function Mnemonic Description Function Instruction Code /No. of Cycles Transfer Transfer MOVA Transfer effective address MOVDir Transfer 4-bit data Restore register/memory POPM Restore multiple registers PUSH Save register/memory/immediate data PUSHA Save effective address PUSHM Save multiple registers...
Page 11 Quick Reference by Function Description Page No. for Page No. for Function Mnemonic Function Instruction Code /No. of Cycles Arithmetic DADD Decimal add without carry Decrement Signed divide DIVU Unsigned divide DIVX Signed divide DSBB Decimal subtract with borrow DSUB Decimal subtract without borrow EXTS Extend sign...
Page 12 Quick Reference by Function Description Page No. for Page No. for Function Mnemonic Function Instruction Code /No. of Cycles Other LDIPL Set interrupt enable level No operation POPC Restore control register PUSHC Save control register REIT Return from interrupt Transfer from control register STCTX Save context Interrupt for undefined instruction...
Page 13 Quick Reference by Addressing Mode (General Instruction Addressing) Addressing Mode Page No. for Page No. for Mnemonic Function Instruction Code /No. of Cycles ADCF ADJNZ DADC DADD DIVU DIVX DSBB DSUB ENTER EXTS JMPI JSRI LDINTB LDIPL 1 Has special instruction addressing. *2 Only R1L can be selected.
Page 14 Quick Reference by Addressing Mode (General Instruction Addressing) Addressing Mode Page No. for Page No. for Mnemonic Function Instruction Code /No. of Cycles MOVA MULU POPM PUSH PUSHA PUSHM ROLC RORC SBJNZ STCTX STNZ *1 Has special instruction addressing. Quick Reference-7...
Page 15 Quick Reference by Addressing Mode (General Instruction Addressing) Addressing Mode Page No. for Page No. for Mnemonic Function Instruction Code /No. of Cycles STZX XCHG Quick Reference-8...
Page 16 Quick Reference by Addressing Mode (Special Instruction Addressing) Page No. for Page No. for Addressing Mode Mnemonic Instruction Function Code /No. of Cycles ADJNZ JCnd JMPI JSRI LDCTX LDINTB POPC POPM PUSHC PUSHM SBJNZ STCTX *1 Has general instruction addressing. *2 INTBL and INTBH can be set simultaneously when using the LDINTB instruction.
Page 17 Quick Reference by Addressing Mode (Bit Instruction Addressing) Addressing Mode Page No. for Page No. for Mnemonic Function Instruction Code /No. of Cycles BAND BCLR BNAND BNOR BNOT BNTST BNXOR BSET BTST BTSTC BTSTS BXOR FCLR FSET Quick Reference-10...
Page 18 This page intentionally left blank. Quick Reference-11...
Page 19: Chapter 1 Overview
Chapter 1 Overview 1.1 Features of R8C/Tiny Series 1.2 Address Space 1.3 Register Configuration 1.4 Flag Register (FLG) 1.5 Register Banks 1.6 Internal State after Reset is Cleared 1.7 Data Types 1.8 Data Arrangement 1.9 Instruction Formats 1.10 Vector Tables...
Page 20: Features Of R8C/Tiny Series
1.1 Features of R8C/Tiny Series The R8C/Tiny Series of single-chip microcomputers was developed for embedded applications. The R8C/Tiny Series supports instructions tailored for the C language, with frequently used instructions implemented in one-byte op-code. It thus allows development of efficient programs with reduced memory requirements when using either assembly language or C.
Page 21: Address Space
R8C/Tiny Series, the SFR area extends from 002FF to lower addresses. Addresses from 00400 and below make up the memory area. In some models in the R8C/Tiny Series, the RAM area extends from address 00400 to higher addresses, and the ROM area extends from 0FFFF lower addresses.
Page 22: Register Configuration
Chapter 1 Overview 1.3 Register Configuration 1.3 Register Configuration The central processing unit (CPU) contains the 13 registers shown in figure 1.3.1. Of these registers, R0, R1, R2, R3, A0, A1, and FB each consist of two sets of registers configured as two register banks. b8 b7 R0H (High-order of R0) R0L (Low-order of R0)
Page 23: Address Registers (A0 And A1)
Chapter 1 Overview 1.3 Register Configuration 1.3.2 Address Registers (A0 and A1) The address registers (A0 and A1) are 16-bit registers with functions similar to those of the data regis- ters. These registers are used for address register-based indirect addressing and address register- based relative addressing.
Page 24: Flag Register (Flg)
Chapter 1 Overview 1.4 Flag Register (FLG) 1.4 Flag Register (FLG) Figure 1.4.1 shows the configuration of the flag register (FLG). The function of each flag is described below. 1.4.1 Bit 0: Carry Flag (C Flag) This flag holds bits carried, borrowed, or shifted-out by the arithmetic/logic unit. 1.4.2 Bit 1: Debug Flag (D Flag) This flag enables a single-step interrupt.
Page 25: Bits 12 To 14: Processor Interrupt Priority Level (Ipl)
Chapter 1 Overview 1.4 Flag Register (FLG) 1.4.10 Bits 12 to 14: Processor Interrupt Priority Level (IPL) The processor interrupt priority level (IPL) consists of three bits, enabling specification of eight proces- sor interrupt priority levels from level 0 to level 7. If a requested interrupt’s priority level is higher than the processor interrupt priority level (IPL), the interrupt is enabled.
Page 26: Register Banks
Chapter 1 Overview 1.5 Register Banks 1.5 Register Banks The R8C/Tiny has two register banks, each comprising data registers (R0, R1, R2, and R3), address regis- ters (A0 and A1), and a frame base register (FB). These two register banks are switched by the register bank select flag (B flag) in the flag register (FLG).
Page 27: Internal State After Reset Is Cleared
Chapter 1 Overview 1.6 Internal State after Reset is Cleared 1.6 Internal State after Reset is Cleared The contents of each register after a reset is cleared are as follows. • Data registers (R0, R1, R2, and R3): 0000 • Address registers (A0 and A1): 0000 •...
Page 28: Data Types
Chapter 1 Overview 1.7 Data Types 1.7 Data Types There are four data types: integer, decimal, bit, and string. 1.7.1 Integer An integer can be signed or unsigned. A negative value of a signed integer is represented by two’s complement. Signed byte (8 bit) integer Unsigned byte (8 bit) integer Signed word (16 bit) integer...
Page 29: Decimal
Chapter 1 Overview 1.7 Data Types 1.7.2 Decimal The decimal data type is used by the DADC, DADD, DSBB, and DSUB instructions. Pack format (2 digits) Pack format (4 digits) Figure 1.7.2 Decimal Data Rev.2.00 Oct 17, 2005 page 11 of 263 REJ09B0001-0200...
Page 30: Bits
Chapter 1 Overview 1.7 Data Types 1.7.3 Bits Register bits Figure 1.7.3 shows register bit specification. Register bits can be specified by register directly (bit, Rn or bit, An). Use bit, Rn to specify a bit in a data register (Rn); use bit, An to specify a bit in an address register (An). The bits in each register are assigned bit numbers from 0 to 15, from LSB to MSB.
Page 31 Chapter 1 Overview 1.7 Data Types (1) Bit Specification by Bit, Base Figure 1.7.5 shows the relationship between the memory map and the bit map. Memory bits can be handled as an array of consecutive bits. Bits can be specified by a combination of bit and base.
Page 32 Chapter 1 Overview 1.7 Data Types (2) SB/FB Relative Bit Specification For SB/FB-based relative addressing, use bit 0 of the address that is the sum of the address set in static base register (SB) or frame base register (FB) plus the address set in base as the reference (= 0), and set the desired bit position in bit.
Page 33: String
Chapter 1 Overview 1.7 Data Types 1.7.4 String String data consists of a given length of consecutive byte (8-bit) or word (16-bit) data. This data type can be used in three string instructions: character string backward transfer (SMOVB instruction), character string forward transfer (SMOVF instruction), and specified area initialize (SSTR instruction).
Page 34: Data Arrangement
Chapter 1 Overview 1.8 Data Arrangement 1.8 Data Arrangement 1.8.1 Data Arrangement in Register Figure 1.8.1 shows the relationship between a register’s data size and bit numbers. Nibble (4-bit) data Byte (8-bit) data Word (16-bit) data Long word (32-bit) data Figure 1.8.1 Data Arrangement in Register Rev.2.00 Oct 17, 2005 page 16 of 263...
Page 35: Data Arrangement In Memory
Chapter 1 Overview 1.8 Data Arrangement 1.8.2 Data Arrangement in Memory Figure 1.8.2 shows the data arrangement in memory. Figure 1.8.3 shows some operation examples. DATA DATA(L) DATA(H) Byte (8-bit) data Word (16-bit) data DATA(L) DATA(LL) DATA(M) DATA(LH) DATA(H) DATA(HL) DATA(HH) Long Word (32-bit) data 20-bit (Address) data...
Page 36: Instruction Formats
Chapter 1 Overview 1.9 Instruction Formats 1.9 Instruction Formats The instruction formats can be classified into four types: generic, quick, short, and zero. The number of instruction bytes that can be chosen by a given format is least for the zero format, and increases succes- sively for the short, quick, and generic formats, in that order.
Page 37: Vector Tables
Chapter 1 Overview 1.10 Vector Tables 1.10 Vector Tables Interrupt vector tables are the only vector tables. There are two types of interrupt vector tables: fixed and variable. 1.10.1 Fixed Vector Tables A fixed vector table is an address-fixed vector table. Part of the interrupt vector table is allocated to addresses 0FFDC through 0FFFF .
Page 38: Variable Vector Tables
Chapter 1 Overview 1.10 Vector Tables 1.10.2 Variable Vector Tables A variable vector table is an address-variable vector table. Specifically, this type of vector table is a 256- byte interrupt vector table that uses the value indicated by the interrupt table register (INTB) as the entry address (IntBase).
Page 39 Chapter 2 Addressing Modes 2.1 Addressing Modes 2.2 Guide to This Chapter 2.3 General Instruction Addressing 2.4 Special Instruction Addressing 2.5 Bit Instruction Addressing...
Page 40: Chapter 2 Addressing Modes
2.1 Addressing Modes This section describes the symbols used to represent addressing modes and operations of each address- ing mode. The R8C/Tiny Series has three types of addressing modes as outlined below. 2.1.1 General Instruction Addressing This addressing mode type accesses the area from address 00000...
Page 41: Guide To This Chapter
Chapter 2 Addressing Modes 2.2 Guide to This Chapter 2.2 Guide to This Chapter An example illustrating how to read this chapter is shown below. Address register relative The value indicated by the displace- dsp:8[A0] ment (dsp) plus the content of the dsp:8[A1] address register (A0/A1)—added Memory...
Page 42: General Instruction Addressing
Chapter 2 Addressing Modes 2.3 General Instruction Addressing 2.3 General Instruction Addressing Immediate #IMM8 The immediate data indicated by #IMM #IMM is the object of the operation. #IMM8 #IMM16 #IMM16 #IMM20 #IMM20 Register direct Register The specified register is the object of the operation.
Page 43 Chapter 2 Addressing Modes 2.3 General Instruction Addressing Address register relative The value indicated by the displace- dsp:8[A0] Memory ment (dsp) plus the content of the dsp:8[A1] address register (A0/A1)—added dsp:16[A0] without the sign bits—is the effective Register address for the operation. dsp:16[A1] A0 / A1 address...
Page 44 Chapter 2 Addressing Modes 2.3 General Instruction Addressing Stack pointer relative dsp:8[SP] The address indicated by the content of the Memory stack pointer (SP) plus the value indicated by If the dsp value is negative the displacement (dsp)—added including the sign bits—is the effective address for the operation.
Page 45: Special Instruction Addressing
Chapter 2 Addressing Modes 2.4 Special Instruction Addressing 2.4 Special Instruction Addressing 20-bit absolute The value indicated by abs20 is the abs20 Memory effective address for the operation. The effective address range is 00000 FFFFF abs20 This addressing mode can be used with the LDE, STE, JSR, and JMP instructions.
Page 46 Chapter 2 Addressing Modes 2.4 Special Instruction Addressing 32-bit register direct SHL, SHA instructions The 32-bit concatenated register content of two R2R0 specified registers is the object of the operation. R2R0 R3R1 R3R1 A1A0 This addressing mode can be used with the SHL, SHA, JMPI, and JSRI instructions.
Page 47 Chapter 2 Addressing Modes 2.4 Special Instruction Addressing Program counter relative • If the jump length specifier (.length) label is (.S), the base address plus the Memory value indicated by the displacement (dsp)—added without the sign bits—is Base address the effective address. This addressing mode can be used with the JMP instruction.
Page 48: Bit Instruction Addressing
Chapter 2 Addressing Modes 2.5 Bit Instruction Addressing 2.5. Bit Instruction Addressing This addressing mode type can be used with the following instructions: BCLR, BSET, BNOT, BTST, BNTST, BAND, BNAND, BOR, BNOR, BXOR, BNXOR, BM , BTSTS, BTSTC Register direct The specified register bit is the object bit,R0 of the operation.
Page 49 Chapter 2 Addressing Modes 2.5 Bit Instruction Addressing Address register relative base:8[A0] The bit that is the number of bits base:8[A1] indicated by the address register base:16[A0] (A0/A1) away from bit 0 at the address indicated by base is the base:16[A1] object of the operation.
Page 50 Chapter 2 Addressing Modes 2.5 Bit Instruction Addressing FB relative The bit that is the number of bits bit,base:8[FB] Memory indicated by bit away from bit 0 at the address indicated by the frame base If the base value is negative register (FB) plus the value indicated by base (added including the sign bit) is the object of the operation.
Page 51: Chapter 3 Functions
Chapter 3 Functions 3.1 Guide to This Chapter 3.2 Functions...
Page 52: Guide To This Chapter
Chapter 3 Functions 3.1 Guide to This Chapter 3.1 Guide to This Chapter In this chapter each instruction’s syntax, operation, function, selectable src/dest, and flag changes are listed, and description examples and related instructions are shown. An example illustrating how to read this chapter is shown below. Chapter 3 Functions 3.2 Functions Transfer...
Page 53 Chapter 3 Functions 3.1 Guide to This Chapter (1) Mnemonic The mnemonic explained in the page. (2) Instruction Code/Number of Cycles The page on which the instruction code and number of cycles is listed. Refer to this page for information on the instruction code and number of cycles. (3) Syntax The syntax of the instruction using symbols.
Page 54 Chapter 3 Functions 3.1 Guide to This Chapter Chapter 3 Functions 3.2 Functions Transfer MOVe [ Instruction Code/Number of Cycles ] [ Syntax ] Page: 193 MOV.size (:format) src,dest G , Q , Z , S (Can be specified) B , W [ Operation ] dest [ Function ]...
Page 55 Chapter 3 Functions 3.1 Guide to This Chapter (4) Operation Explains the operation of the instruction using symbols. (5) Function Explains the function of the instruction and precautions to be taken when using the instruction. (6) Selectable src / dest (label) If the instruction has operands, the valid formats are listed here.
Page 56 Chapter 3 Functions 3.1 Guide to This Chapter The syntax of the jump instructions JMP, JPMI, JSR, and JSRI are illustrated below by example . Chapter 3 Functions 3.2 Functions Unconditional jump JuMP [ Instruction Code/Number of Cycles ] [ Syntax ] Page: 183 JMP (.length) label S, B, W, A (Can be specified)
Page 57: Functions
Chapter 3 Functions Functions Absolute value ABSolute [ Syntax ] [ Instruction Code/Number of Cycles ] ABS.size dest Page: 138 B , W [ Operation ] dest dest [ Function ] dest dest • This instruction takes the absolute value of and stores it in [ Selectable dest ] dest...
Page 58 Chapter 3 Functions Functions Add with carry ADdition with Carry [ Syntax ] [ Instruction Code/Number of Cycles ] ADC.size src,dest Page: 138 B , W [ Operation ] dest dest [ Function ] dest dest • This instruction adds , and the C flag and stores the result in dest •...
Page 59: Adcf
Chapter 3 Functions Functions Add carry flag ADCF ADCF ADdition Carry Flag [ Syntax ] [ Instruction Code/Number of Cycles ] ADCF.size dest Page: 140 B , W [ Operation ] dest dest [ Function ] dest dest This instruction adds and the C flag and stores the result in [ Selectable dest ] dest...
Page 60 Chapter 3 Functions Functions Add without carry ADDition [ Syntax ] [ Instruction Code/Number of Cycles ] ADD.size (:format) src,dest Page: 140 G , Q , S (Can be specified) B , W [ Operation ] dest dest [ Function ] dest dest •...
Page 61 Chapter 3 Functions Functions [src/dest Classified by Format] G format dest R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:20[A0] dsp:20[A1] abs20 #IMM...
Page 62: Adjnz
Chapter 3 Functions Functions Add and conditional jump ADJNZ ADJNZ ADdition then Jump on Not Zero [ Syntax ] [ Instruction Code/Number of Cycles ] ADJNZ.size src,dest,label Page: 146 B , W [ Operation ] dest dest if dest 0 then jump label [ Function ] dest dest...
Page 63 Chapter 3 Functions Functions Logically AND [ Syntax ] [ Instruction Code/Number of Cycles ] AND.size (:format) src,dest Page: 147 G , S (Can be specified) B , W [ Operation ] dest dest [ Function ] dest dest • This instruction logically ANDs and stores the result in dest •...
Page 64 Chapter 3 Functions Functions [src/dest Classified by Format] G format dest R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:20[A0] dsp:20[A1] abs20 #IMM...
Page 65: Band
Chapter 3 Functions Functions Logically AND bits BAND BAND Bit AND carry flag [ Syntax ] [ Instruction Code/Number of Cycles ] BAND src Page: 150 [ Operation ] [ Function ] • This instruction logically ANDs the C flag and and stores the result in the C flag.
Page 66: Bclr
Chapter 3 Functions Functions Clear bit BCLR BCLR Bit CLeaR [ Syntax ] [ Instruction Code/Number of Cycles ] BCLR (:format) dest Page: 150 G , S (Can be specified) [ Operation ] dest [ Function ] dest • This instruction stores 0 in [ Selectable dest ] dest bit,R0...
Page 67: Bmcnd
Chapter 3 Functions Functions Conditional bit transfer BM Cnd BM Cnd Bit Move Condition [ Syntax ] [ Instruction Code/Number of Cycles ] BM Cnd dest Page: 152 [ Operation ] if true then dest else dest [ Function ] dest •...
Page 68: Bnand
Chapter 3 Functions Functions Logically AND inverted bits BNAND BNAND Bit Not AND carry flag [ Syntax ] [ Instruction Code/Number of Cycles ] BNAND Page: 153 [ Operation ] ______ [ Function ] • This instruction logically ANDs the C flag and the inverted value of and stores the result in the C flag.
Page 69: Bnor
Chapter 3 Functions 3.2 Functions Logically OR inverted bits BNOR BNOR Bit Not OR carry flag [ Syntax ] [ Instruction Code/Number of Cycles ] BNOR src Page: 154 [ Operation ] ______ [ Function ] • This instruction logically ORs the C flag and the inverted value of and stores the result in the C flag.
Page 70: Bnot
Chapter 3 Functions 3.2 Functions Invert bit BNOT BNOT Bit NOT [ Syntax ] [ Instruction Code/Number of Cycles ] BNOT(:format) dest Page: 154 G , S (Can be specified) [ Operation ] ________ dest dest [ Function ] dest dest •...
Page 71: Bntst
Chapter 3 Functions 3.2 Functions Test inverted bit BNTST BNTST Bit Not TeST [ Syntax ] [ Instruction Code/Number of Cycles ] BNTST Page: 155 [ Operation ] ______ [ Function ] • This instruction transfers the inverted value of to the Z flag and the inverted value of to the C flag.
Page 72: Bnxor
Chapter 3 Functions 3.2 Functions Exclusive OR inverted bits BNXOR BNXOR Bit Not eXclusive OR carry flag [ Syntax ] [ Instruction Code/Number of Cycles ] BNXOR Page: 156 [ Operation ] ______ [ Function ] • This instruction exclusive ORs the C flag and the inverted value of and stores the result in the C flag.
Page 73 Chapter 3 Functions 3.2 Functions Logically OR bits Bit OR carry flag [ Syntax ] [ Instruction Code/Number of Cycles ] Page: 156 [ Operation ] [ Function ] • This instruction logically ORs the C flag and and stores the result in the C flag. [ Selectable src ] bit,R0 bit,R1...
Page 74 Chapter 3 Functions 3.2 Functions Debug interrupt BReaK [ Syntax ] [ Instruction Code/Number of Cycles ] Page: 157 [ Operation ] – M(SP) , FLG – M(SP) M(FFFE4 [ Function ] • This instruction generates a BRK interrupt. • The BRK interrupt is a nonmaskable interrupt. [ Flag Change ] Flag *1 The flags are saved to the stack area before the BRK in-...
Page 75: Bset
Chapter 3 Functions 3.2 Functions Set bit BSET BSET Bit SET [ Syntax ] [ Instruction Code/Number of Cycles ] BSET (:format) dest Page: 157 G , S (Can be specified) [ Operation ] dest [ Function ] dest • This instruction stores 1 in [ Selectable dest ] dest bit,R0...
Page 76: Btst
Chapter 3 Functions 3.2 Functions Test bit BTST BTST Bit TeST [ Syntax ] [ Instruction Code/Number of Cycles ] BTST (:format) Page: 158 G , S (Can be specified) [ Operation ] ______ [ Function ] • This instruction transfers the inverted value of to the Z flag and the non-inverted value of the C flag.
Page 77: Btstc
Chapter 3 Functions 3.2 Functions Test bit and clear BTSTC BTSTC Bit TeST and Clear [ Syntax ] [ Instruction Code/Number of Cycles ] BTSTC dest Page: 159 [ Operation ] ________ dest dest dest [ Function ] dest • This instruction transfers the inverted value of to the Z flag and the non-inverted value of dest dest...
Page 78: Btsts
Chapter 3 Functions 3.2 Functions Test bit and set BTSTS BTSTS Bit TeST and Set [ Syntax ] [ Instruction Code/Number of Cycles ] BTSTS dest Page: 160 [ Operation ] ________ dest dest dest [ Function ] dest dest •...
Page 79: Bxor
Chapter 3 Functions 3.2 Functions Exclusive OR bits BXOR BXOR Bit eXclusive OR carry flag [ Syntax ] [ Instruction Code/Number of Cycles ] BXOR src Page: 160 [ Operation ] [ Function ] • This instruction exclusive ORs the C flag and and stores the result in the C flag.
Page 80 Chapter 3 Functions 3.2 Functions Compare CoMPare [ Syntax ] [ Instruction Code/Number of Cycles ] CMP.size (:format) src,dest Page: 161 G , Q , S (Can be specified) B , W [ Operation ] dest – [ Function ] dest •...
Page 81 Chapter 3 Functions 3.2 Functions [src/dest Classified by Format] G format dest R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:20[A0] dsp:20[A1] abs20...
Page 82: Dadc
Chapter 3 Functions 3.2 Functions Decimal add with carry DADC DADC Decimal ADdition with Carry [ Instruction Code/Number of Cycles ] [ Syntax ] Page: 165 DADC.size src,dest B , W [ Operation ] dest dest [ Function ] dest dest •...
Page 83: Dadd
Chapter 3 Functions 3.2 Functions Decimal add without carry DADD DADD Decimal ADDition [ Syntax ] [ Instruction Code/Number of Cycles ] DADD.size src,dest Page: 167 B , W [ Operation ] dest dest [ Function ] dest dest • This instruction adds as decimal data and stores the result in [ Selectable src/dest ] dest...
Page 84 Chapter 3 Functions 3.2 Functions Decrement DECrement [ Syntax ] [ Instruction Code/Number of Cycles ] DEC.size dest Page: 169 B , W [ Operation ] dest dest – [ Function ] dest dest • This instruction decrements by 1 and stores the result in [ Selectable dest ] dest dsp:8[SB]...
Page 85 Chapter 3 Functions 3.2 Functions Signed divide DIVide [ Syntax ] [ Instruction Code/Number of Cycles ] DIV.size Page: 170 B , W [ Operation ] If the size specifier (.size) is (.B) R0L (quotient), R0H (remainder) If the size specifier (.size) is (.W) R0 (quotient), R2 (remainder) R2R0 [ Function ]...
Page 86 Chapter 3 Functions 3.2 Functions Unsigned divide DIVU DIVU DIVide Unsigned [ Syntax ] [ Instruction Code/Number of Cycles ] DIVU.size Page: 171 B , W [ Operation ] If the size specifier (.size) is (.B) R0L (quotient), R0H (remainder) If the size specifier (.size) is (.W) R0 (quotient), R2 (remainder) R2R0...
Page 87 Chapter 3 Functions 3.2 Functions Signed divide DIVX DIVX DIVide eXtension [ Syntax ] [ Instruction Code/Number of Cycles ] DIVX.size Page: 172 B , W [ Operation ] If the size specifier (.size) is (.B) R0L (quotient), R0H (remainder) If the size specifier (.size) is (.W) R0 (quotient), R2 (remainder) R2R0...
Page 88 Chapter 3 Functions 3.2 Functions Decimal subtract with borrow DSBB DSBB Decimal SuBtract with Borrow [ Syntax ] [ Instruction Code/Number of Cycles ] DSBB.size src,dest Page: 173 B , W [ Operation ] ____ dest dest – – [ Function ] dest •...
Page 89 Chapter 3 Functions 3.2 Functions Decimal subtract without borrow DSUB DSUB Decimal SUBtract [ Instruction Code/Number of Cycles ] [ Syntax ] Page: 175 DSUB.size src,dest B , W [ Operation ] dest dest – [ Function ] dest dest •...
Page 90 Chapter 3 Functions 3.2 Functions Build stack frame ENTER ENTER ENTER function [ Syntax ] [ Instruction Code/Number of Cycles ] ENTER Page: 177 [ Operation ] – M(SP) – [ Function ] • This instruction generates a stack frame. represents the size of the stack frame.
Page 91 Chapter 3 Functions 3.2 Functions Deallocate stack frame EXITD EXITD EXIT and Deallocate stack frame [ Instruction Code/Number of Cycles ] [ Syntax ] Page: 178 EXITD [ Operation ] M(SP) M(SP) M(SP) [ Function ] • This instruction deallocates a stack frame and exits from the subroutine. •...
Page 92 Chapter 3 Functions 3.2 Functions Extend sign EXTS EXTS EXTend Sign [ Instruction Code/Number of Cycles ] [ Syntax ] Page: 178 EXTS.size dest B , W [ Operation ] dest EXT(dest) [ Function ] dest dest • This instruction sign extends and stores the result in dest •...
Page 93 Chapter 3 Functions 3.2 Functions Clear flag register bit FCLR FCLR Flag register CLeaR [ Syntax ] [ Instruction Code/Number of Cycles ] FCLR dest Page: 179 [ Operation ] dest [ Function ] dest • This instruction stores 0 in [ Selectable dest ] dest [ Flag Change ]...
Page 94 Chapter 3 Functions 3.2 Functions Set flag register bit FSET FSET Flag register SET [ Syntax ] [ Instruction Code/Number of Cycles ] FSET dest Page: 180 [ Operation ] dest [ Function ] dest • This instruction stores 1 in [ Selectable dest ] dest [ Flag Change ]...
Page 95 Chapter 3 Functions 3.2 Functions Increment INCrement [ Syntax ] [ Instruction Code/Number of Cycles ] INC.size dest Page: 180 B , W [ Operation ] dest dest [ Function ] dest dest • This instruction adds 1 to and stores the result in [ Selectable dest ] dest dsp:8[SB]...
Page 96 Chapter 3 Functions 3.2 Functions Interrupt by INT instruction INTerrupt [ Syntax ] [ Instruction Code/Number of Cycles ] Page: 181 [ Operation ] SP – M(SP) , FLG – M(SP) M(IntBase [ Function ] • This instruction generates a software interrupt specified by represents a software interrupt number.
Page 97 Chapter 3 Functions 3.2 Functions Interrupt on overflow INTO INTO INTerrupt on Overflow [ Syntax ] [ Instruction Code/Number of Cycles ] INTO Page: 182 [ Operation ] SP – M(SP) , FLG – M(SP) M(FFFE0 [ Function ] • If the O flag is set to 1, this instruction generates an overflow interrupt. If the flag is cleared to 0, the next instruction is executed.
Page 98 Chapter 3 Functions 3.2 Functions Jump on condition J Cnd J Cnd Jump on Condition [ Syntax ] [ Instruction Code/Number of Cycles ] J Cnd label Page: 182 [ Operation ] if true then jump label [ Function ] •...
Page 99 Chapter 3 Functions 3.2 Functions Unconditional jump JuMP [ Syntax ] [ Instruction Code/Number of Cycles ] JMP(.length) label Page: 184 S , B , W , A (Can be specified) [ Operation ] label [ Function ] • This instruction causes control to jump to label. [ Selectable label ] .length label...
Page 100 Chapter 3 Functions 3.2 Functions Jump indirect JMPI JMPI JuMP Indirect [ Syntax ] [ Instruction Code/Number of Cycles ] JMPI.length Page: 185 W , A [ Operation ] When jump distance specifier (.length) is (.W) When jump distance specifier (.length) is (.A) [ Function ] •...
Page 101 Chapter 3 Functions 3.2 Functions Subroutine call Jump SubRoutine [ Instruction Code/Number of Cycles ] [ Syntax ] Page: 187 JSR(.length) label W , A (Can be specified) [ Operation ] – M(SP) – M(SP) label n denotes the number of instruction bytes. [ Function ] •...
Page 102 Chapter 3 Functions 3.2 Functions Indirect subroutine call JSRI JSRI Jump SubRoutine Indirect [ Syntax ] [ Instruction Code/Number of Cycles ] JSRI.length src Page: 188 W , A [ Operation ] When jump distance specifier (.length) is (.W) When jump distance specifier (.length) is (.A) –...
Page 103 Chapter 3 Functions 3.2 Functions Transfer to control register LoaD Control register [ Syntax ] [ Instruction Code/Number of Cycles ] src,dest Page: 189 [ Operation ] dest [ Function ] dest • This instruction transfers to the control register indicated by .
Page 104 Chapter 3 Functions 3.2 Functions Restore context LDCTX LDCTX LoaD ConTeXt [ Syntax ] [ Instruction Code/Number of Cycles ] LDCTX abs16,abs20 Page: 189 [ Function ] • This instruction restores task context from the stack area. • Set the RAM address that contains the task number in abs16 and the start address of table data in abs20. •...
Page 105 Chapter 3 Functions 3.2 Functions Transfer from extended data area LoaD from EXtra far data area [ Syntax ] [ Instruction Code/Number of Cycles ] LDE.size src,dest Page: 191 B , W [ Operation ] dest [ Function ] dest •...
Page 106 Chapter 3 Functions 3.2 Functions Transfer to INTB register LDINTB LDINTB LoaD INTB register [ Syntax ] [ Instruction Code/Number of Cycles ] LDINTB Page: 192 [ Operation ] INTBHL [ Function ] • This instruction transfers to INTB. • The LDINTB instruction is a macro-instruction consisting of the following: #IMM, INTBH #IMM, INTBL [ Selectable src ]...
Page 107 Chapter 3 Functions 3.2 Functions Set interrupt enable level LDIPL LDIPL LoaD Interrupt Permission Level [ Syntax ] [ Instruction Code/Number of Cycles ] LDIPL src Page: 193 [ Operation ] [ Function ] • This instruction transfers to IPL. [ Selectable src ] #IMM *1 The acceptable range of values is 0 <...
Page 108 Chapter 3 Functions 3.2 Functions Transfer MOVe [ Syntax ] [ Instruction Code/Number of Cycles ] MOV.size (:format) src,dest Page: 193 (Can be specified) G , Q , Z , S B , W [ Operation ] dest [ Function ] dest •...
Page 109 Chapter 3 Functions 3.2 Functions [src/dest Classified by Format] G format dest R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:20[A0] dsp:20[A1] abs20...
Page 110 Chapter 3 Functions 3.2 Functions Transfer effective address MOVA MOVA MOVe effective Address [ Syntax ] [ Instruction Code/Number of Cycles ] MOVA src,dest Page: 200 [ Operation ] dest EVA(src) [ Function ] dest • This instruction transfers the affective address of [ Selectable src/dest ] dest R0L/R0...
Page 111: Movhh
Chapter 3 Functions 3.2 Functions Transfer 4-bit data MOV Dir MOV Dir MOVe nibble [ Syntax ] [ Instruction Code/Number of Cycles ] MOV Dir src,dest Page: 201 [ Operation ] Operation H4:dest H4:src L4:dest H4:src H4:dest L4:src L4:dest L4:src [ Function ] dest •...
Page 112 Chapter 3 Functions 3.2 Functions Signed multiply MULtiple [ Syntax ] [ Instruction Code/Number of Cycles ] MUL.size src,dest Page: 203 B , W [ Operation ] dest dest [ Function ] dest dest • This instruction multiplies including the sign bits and stores the result in dest •...
Page 113: Mulu
Chapter 3 Functions 3.2 Functions Unsigned multiply MULU MULU MULtiple Unsigned [ Syntax ] [ Instruction Code/Number of Cycles ] MULU.size src,dest Page: 205 B , W [ Operation ] dest dest [ Function ] dest dest • This instruction multiplies without the sign bits and stores the result in dest •...
Page 114 Chapter 3 Functions 3.2 Functions Complement of two NEGate [ Syntax ] [ Instruction Code/Number of Cycles ] NEG.size dest Page: 207 B , W [ Operation ] dest – dest [ Function ] dest dest • This instruction takes the complement of two of and stores the result in [ Selectable dest ] dest...
Page 115 Chapter 3 Functions 3.2 Functions No operation No OPeration [ Syntax ] [ Instruction Code/Number of Cycles ] Page: 207 [ Operation ] [ Function ] • This instruction adds 1 to PC. [ Flag Change ] Flag Change [ Description Example ] Rev.2.00 Oct 17, 2005 page 97 of 263 REJ09B0001-0200...
Page 116 Chapter 3 Functions 3.2 Functions Invert all bits [ Syntax ] [ Instruction Code/Number of Cycles ] NOT.size (:format) dest Page: 208 (Can be specified) G , S B , W [ Operation ] ________ dest dest [ Function ] dest dest •...
Page 117 Chapter 3 Functions Functions Logically OR [ Syntax ] [ Instruction Code/Number of Cycles ] OR.size (:format) src,dest Page: 209 G , S (Can be specified) B , W [ Operation ] dest dest [ Function ] dest dest • This instruction logically ORs and stores the result in dest •...
Page 118 Chapter 3 Functions Functions [src/dest Classified by Format] G format dest R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:20[A0] dsp:20[A1] abs20 #IMM...
Page 119 Chapter 3 Functions Functions Restore register/memory [ Syntax ] [ Instruction Code/Number of Cycles ] POP.size (:format) dest Page: 211 G , S (Can be specified) B , W [ Operation ] If the size specifier (.size) is (.B) If the size specifier (.size) is (.W) dest M(SP) dest...
Page 120: Popc
Chapter 3 Functions Functions Restore control register POPC POPC POP Control register [ Syntax ] [ Instruction Code/Number of Cycles ] POPC dest Page: 213 [ Operation ] dest M(SP) dest dest *1 When is SP or when the U flag = 0 and is ISP, 2 is not added to SP.
Page 121: Popm
Chapter 3 Functions Functions Restore multiple registers POPM POPM POP Multiple [ Syntax ] [ Instruction Code/Number of Cycles ] POPM dest Page: 213 [ Operation ] dest M(SP) *1 Number of registers to be restored [ Function ] dest •...
Page 122: Push
Chapter 3 Functions Functions Save register/memory/immediate data PUSH PUSH PUSH [ Syntax ] [ Instruction Code/Number of Cycles ] PUSH.size (:format) Page: 214 G , S (Can be specified) B , W [ Operation ] If the size specifier (.size) is (.W) If the size specifier (.size) is (.B) –...
Page 123: Pusha
Chapter 3 Functions Functions Save effective address PUSHA PUSHA PUSH effective Address [ Syntax ] [ Instruction Code/Number of Cycles ] PUSHA Page: 216 [ Operation ] – M(SP) EVA(src) [ Function ] • This instruction saves the effective address of to the stack area.
Page 124: Pushc
Chapter 3 Functions Functions Save control register PUSHC PUSHC PUSH Control register [ Syntax ] [ Instruction Code/Number of Cycles ] PUSHC Page: 216 [ Operation ] – M(SP) *1 When is SP or when the U flag = 0 and is ISP, SP is saved before 2 is subtracted.
Page 125: Pushm
Chapter 3 Functions Functions Save multiple registers PUSHM PUSHM PUSH Multiple [ Syntax ] [ Instruction Code/Number of Cycles ] PUSHM Page: 217 [ Operation ] – M(SP) *1 Number of registers saved. [ Function ] • This instruction saves the registers selected by collectively to the stack area.
Page 126: Reit
Chapter 3 Functions Functions Return from interrupt REIT REIT REturn from InTerrupt [ Syntax ] [ Instruction Code/Number of Cycles ] REIT Page: 218 [ Operation ] M(SP) , FLG M(SP) [ Function ] • This instruction restores the PC and FLG values that were saved when an interrupt request was accepted and returns from the interrupt handler routine.
Page 127: Rmpa
Chapter 3 Functions Functions Calculate sum-of-products RMPA RMPA Repeat MultiPle and Addition [ Syntax ] [ Instruction Code/Number of Cycles ] RMPA.size Page: 218 B , W [ Operation ] Repeat R2R0(R0) R2R0(R0) M(A0) M(A1) 2 (1) 2 (1) – Until R3 = 0 If R3 is set to 0, this instruction is ignored.
Page 128: Rolc
Chapter 3 Functions Functions Rotate left with carry ROLC ROLC ROtate to Left with Carry [ Syntax ] [ Instruction Code/Number of Cycles ] ROLC.size dest Page: 218 B , W [ Operation ] dest [ Function ] dest • This instruction rotates one bit to the left including the C flag.
Page 129: Rorc
Chapter 3 Functions Functions Rotate right with carry RORC RORC ROtate to Right with Carry [ Syntax ] [ Instruction Code/Number of Cycles ] RORC.size dest Page: 219 B , W [ Operation ] dest [ Function ] dest • This instruction rotates one bit to the right including the C flag.
Page 130 Chapter 3 Functions Functions Rotate ROTate [ Syntax ] [ Instruction Code/Number of Cycles ] ROT.size src,dest Page: 220 B , W [ Operation ] src<0 dest src>0 [ Function ] dest • This instruction rotates left or right the number of bits indicated by .
Page 131 Chapter 3 Functions Functions Return from subroutine ReTurn from Subroutine [ Syntax ] [ Instruction Code/Number of Cycles ] Page: 221 [ Operation ] M(SP) M(SP) [ Function ] • This instruction causes control to return from a subroutine. [ Flag Change ] Flag Change [ Description Example ]...
Page 132 Chapter 3 Functions Functions Subtract with borrow SuBtract with Borrow [ Instruction Code/Number of Cycles ] [ Syntax ] Page: 222 SBB.size src,dest B , W [ Operation ] dest dest – – [ Function ] dest dest • This instruction subtracts and the inverted value of the C flag from and stores the result in dest...
Page 133 Chapter 3 Functions Functions Subtract and conditional jump SBJNZ SBJNZ SuBtract then Jump on Not Zero [ Syntax ] [ Instruction Code/Number of Cycles ] SBJNZ.size src,dest,label Page: 224 B , W [ Operation ] dest dest – if dest 0 then jump label [ Function ] dest dest...
Page 134 Chapter 3 Functions Functions Shift arithmetic SHift Arithmetic [ Syntax ] [ Instruction Code/Number of Cycles ] SHA.size src,dest Page: 225 B , W , L [ Operation ] When < 0 dest When > 0 dest [ Function ] dest •...
Page 135 Chapter 3 Functions Functions Shift logical SHift Logical [ Syntax ] [ Instruction Code/Number of Cycles ] SHL.size src,dest Page: 228 B , W , L [ Operation ] dest When < 0 dest When > 0 [ Function ] dest •...
Page 136 Chapter 3 Functions Functions Transfer string backward SMOVB SMOVB String MOVe Backward [ Syntax ] [ Instruction Code/Number of Cycles ] SMOVB.size Page: 230 B , W [ Operation ] When size specifier (.size) is (.B) When size specifier (.size) is (.W) Repeat Repeat M(A1)
Page 137 Chapter 3 Functions Functions Transfer string forward SMOVF SMOVF String MOVe Forward [ Syntax ] [ Instruction Code/Number of Cycles ] SMOVF.size Page: 231 B , W [ Operation ] When size specifier (.size) is (.B) When size specifier (.size) is (.W) Repeat Repeat M(A1)
Page 138 Chapter 3 Functions Functions Store string SSTR SSTR String SToRe [ Syntax ] [ Instruction Code/Number of Cycles ] SSTR.size Page: 231 B , W [ Operation ] When size specifier (.size) is (.B) When size specifier (.size) is (.W) Repeat Repeat M(A1)
Page 139 Chapter 3 Functions Functions Transfer from control register STore from Control register [ Instruction Code/Number of Cycles ] [ Syntax ] Page: 232 src,dest [ Operation ] dest [ Function ] dest dest • This instruction transfers the content of the control register indicated by .
Page 140 Chapter 3 Functions Functions Save context STCTX STCTX STore ConTeXt [ Syntax ] [ Instruction Code/Number of Cycles ] STCTX abs16,abs20 Page: 233 [ Operation ] [ Function ] • This instruction saves task context to the stack area. • Set the RAM address that contains the task number in abs16 and the start address of table data in abs20. •...
Page 141 Chapter 3 Functions Functions Transfer to extended data area STore to EXtra far data area [ Syntax ] [ Instruction Code/Number of Cycles ] STE.size src,dest Page: 233 B , W [ Operation ] dest [ Function ] dest • This instruction transfers in an extended area.
Page 142 Chapter 3 Functions Functions Conditional transfer STNZ STNZ STore on Not Zero [ Syntax ] [ Instruction Code/Number of Cycles ] STNZ src,dest Page: 235 [ Operation ] if Z = 0 then dest [ Function ] dest • This instruction transfers when the Z flag is 0.
Page 143 Chapter 3 Functions Functions Conditional transfer STore on Zero [ Syntax ] [ Instruction Code/Number of Cycles ] src,dest Page: 235 [ Operation ] if Z = 1 then dest [ Function ] dest • This instruction transfers when the Z flag is 1. [ Selectable src/dest ] dest #IMM8...
Page 144 Chapter 3 Functions Functions Conditional transfer STZX STZX STore on Zero eXtention [ Syntax ] [ Instruction Code/Number of Cycles ] STZX src1,src2,dest Page: 236 [ Operation ] If Z = 1 then dest src1 else dest src2 [ Function ] src1 dest src2...
Page 145 Chapter 3 Functions Functions Subtract without borrow SUBtract [ Syntax ] [ Instruction Code/Number of Cycles ] SUB.size (:format) src,dest Page: 236 G , S (Can be specified) B , W [ Operation ] dest dest – [ Function ] dest dest •...
Page 146 Chapter 3 Functions Functions [src/dest Classified by Format] G format dest R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3 A0/A0 A1/A1 [A0] [A1] A0/A0 A1/A1 [A0] [A1] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:20[A0] dsp:20[A1] abs20 #IMM...
Page 147 Chapter 3 Functions Functions Test TeST [ Syntax ] [ Instruction Code/Number of Cycles ] TST.size src,dest Page: 239 B , W [ Operation ] dest [ Function ] dest • Each flag in the flag register changes state depending on the result of a logical AND of dest •...
Page 148 Chapter 3 Functions Functions Interrupt for undefined instruction UNDefined instruction [ Syntax ] [ Instruction Code/Number of Cycles ] Page: 241 [ Operation ] – M(SP) , FLG – M(SP) M(FFFDC [ Function ] • This instruction generates an undefined instruction interrupt. •...
Page 149 Chapter 3 Functions Functions Wait WAIT WAIT WAIT [ Syntax ] [ Instruction Code/Number of Cycles ] WAIT Page: 241 [ Operation ] [ Function ] • This instruction halts program execution. Program execution is restarted when an interrupt of a higher priority level than IPL is acknowledged or a reset is generated.
Page 150 Chapter 3 Functions Functions Exchange XCHG XCHG eXCHanGe [ Syntax ] [ Instruction Code/Number of Cycles ] XCHG.size src,dest Page: 242 B , W [ Operation ] dest [ Function ] dest • This instruction exchanges the contents of dest •...
Page 151 Chapter 3 Functions Functions Exclusive OR eXclusive OR [ Syntax ] [ Instruction Code/Number of Cycles ] XOR.size src,dest Page: 243 B , W [ Operation ] dest dest [ Function ] dest dest • This instruction exclusive ORs and stores the result in dest •...
Page 152 Chapter 3 Functions Functions This page intentionally left blank. Rev.2.00 Oct 17, 2005 page 134 of 263 REJ09B0001-0200...
Page 153: Chapter 4 Instruction Codes/Number Of Cycles
Chapter 4 Instruction Codes/Number of Cycles 4.1 Guide to This Chapter 4.2 Instruction Codes/Number of Cycles...
Page 154: Guide To This Chapter
Chapter 4 Instruction Codes Guide to This Chapter 4.1 Guide to This Chapter This chapter lists the instruction code and number of cycles for each op-code. An example illustrating how to read this chapter is shown below. Chapter 4 Instruction Code Instruction Codes/Number of Cycles LDIPL (1) LDIPL #IMM...
Page 155 Chapter 4 Instruction Codes Guide to This Chapter (1) Mnemonic Shows the mnemonic explained in the page. (2) Syntax Shows an instruction syntax using symbols. (3) Instruction code Shows instruction code. Portions in parentheses ( ) may be omitted depending on the selected src/dest. Contents at addresses following Content at start address (start address of instruction + 2)
Page 156: Instruction Codes/Number Of Cycles
Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (1) ABS.size dest dest code b0 b7 dsp8 0 1 1 1 0 1 1 SIZE 1 1 1 1 DEST dsp16/abs16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0 dsp:8[An]...
Page 157 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (2) ADC.size src, dest src code dest code b0 b7 dsp8 dsp8 1 0 1 1 0 0 0 SIZE DEST dsp16/abs16 dsp16/abs16 .size SIZE src/dest src/dest SRC/DEST SRC/DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 158 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles ADCF (1) ADCF.size dest dest code b0 b7 dsp8 0 1 1 1 0 1 1 SIZE 1 1 1 0 DEST dsp16/abs16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 159 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (2) ADD.size:Q #IMM, dest dest code b0 b7 dsp8 1 1 0 0 1 0 0 SIZE IMM4 DEST dsp16/abs16 .size SIZE #IMM IMM4 IMM4 #IMM 0 0 0 0 1 0 0 0 –8 0 0 0 1...
Page 160 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (3) ADD.B:S #IMM8, dest dest code #IMM8 dsp8 1 0 0 0 0 DEST abs16 dest DEST 0 1 1 1 0 0 dsp:8[SB] 1 0 1 dsp:8[SB/FB] dsp:8[FB] 1 1 0 abs16 abs16 1 1 1...
Page 161 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (4) ADD.size:G src, dest src code dest code b0 b7 dsp8 dsp8 1 0 1 0 0 0 0 SIZE DEST dsp16/abs16 dsp16/abs16 .size SIZE src/dest src/dest SRC/DEST SRC/DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 162 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (5) ADD.B:S src, R0L/R0H src code dsp8 0 0 1 0 0 DEST SRC abs16 dest DEST R0L/R0H dsp:8[SB] dsp:8[SB/FB] dsp:8[FB] abs16 abs16 [ Number of Bytes/Number of Cycles ] dsp:8[SB/FB] abs16 Bytes/Cycles...
Page 163 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (7) ADD.size:Q #IMM, SP b0 b7 0 1 1 1 1 1 0 1 1 0 1 1 IMM4 • The instruction code is the same regardless of whether (.B) or (.W) is selected as the size specifier (.size). #IMM IMM4 IMM4...
Page 164 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles ADJNZ (1) ADJNZ.size #IMM, dest, label dest code label code b0 b7 dsp8 dsp8 1 1 1 1 1 0 0 SIZE IMM4 DEST dsp16/abs16 dsp8 (label code) = address indicated by label – (start address of instruction + 2) .size SIZE #IMM...
Page 165 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (1) AND.size:G #IMM, dest dest code b0 b7 0 1 1 1 0 1 1 SIZE 0 0 1 0 DEST dsp8 #IMM8 dsp16/abs16 #IMM16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0...
Page 166 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (3) AND.size:G src, dest src code dest code b0 b7 1 0 0 1 0 0 0 SIZE DEST dsp8 dsp8 dsp16/abs16 dsp16/abs16 .size SIZE src/dest src/dest SRC/DEST SRC/DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 167 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (4) AND.B:S src, R0L/R0H src code 0 0 0 1 0 DEST SRC dsp8 abs16 dest DEST R0L/R0H dsp:8[SB] dsp:8[SB/FB] dsp:8[FB] abs16 abs16 [ Number of Bytes/Number of Cycles ] dsp:8[SB/FB] abs16 Bytes/Cycles...
Page 168 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles BAND (1) BAND src code b0 b7 0 1 1 1 1 1 1 0 0 1 0 0 dsp8 dsp16 bit,R0 0 0 0 0 base:8[A0] 1 0 0 0 base:8[An] bit,R1 0 0 0 1...
Page 169 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles BCLR (2) BCLR:S bit, base:11[SB] dest code 0 1 0 0 0 dsp8 [ Number of Bytes/Number of Cycles ] Bytes/Cycles Rev.2.00 Oct 17, 2005 page 151 of 263 REJ09B0001-0200...
Page 170 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles BM Cnd (1) BM Cnd dest dest code b0 b7 dsp8 0 1 1 1 1 1 1 0 0 0 1 0 DEST dsp16 dest dest DEST DEST bit,R0 0 0 0 0 base:8[A0] 1 0 0 0...
Page 171 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles BM Cnd (2) BM Cnd b0 b7 0 1 1 1 1 1 0 1 1 1 0 1 GEU/C 0 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 EQ/Z 0 0 1 0...
Page 172 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles BNOR (1) BNOR src code b0 b7 dsp8 0 1 1 1 1 1 1 0 0 1 1 1 dsp16 bit,R0 0 0 0 0 base:8[A0] 1 0 0 0 base:8[An] bit,R1 0 0 0 1...
Page 173 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles BNOT (2) BNOT:S bit, base:11[SB] dest code 0 1 0 1 0 dsp8 [ Number of Bytes/Number of Cycles ] Bytes/Cycles BNTST (1) BNTST src code b0 b7 dsp8 0 1 1 1 1 1 1 0 0 0 1 1 dsp16 bit,R0 0 0 0 0...
Page 174 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles BNXOR (1) BNXOR src src code b0 b7 dsp8 0 1 1 1 1 1 1 0 1 1 0 1 dsp16 bit,R0 0 0 0 0 base:8[A0] 1 0 0 0 base:8[An] bit,R1 0 0 0 1...
Page 175 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (1) BRK 0 0 0 0 0 0 0 0 [ Number of Bytes/Number of Cycles ] Bytes/Cycles 1/27 • If the target address of the BRK interrupt is specified using the interrupt table register (INTB), the number of cycles shown in the table increases by two.
Page 176 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles BSET (2) BSET:S bit, base:11[SB] dest code 0 1 0 0 1 dsp8 [ Number of Bytes/Number of Cycles ] Bytes/Cycles BTST (1) BTST:G src src code b0 b7 0 1 1 1 1 1 1 0 1 0 1 1 dsp8 dsp16 bit,R0...
Page 177 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles BTST (2) BTST:S bit, base:11[SB] src code 0 1 0 1 1 dsp8 [ Number of Bytes/Number of Cycles ] Bytes/Cycles BTSTC (1) BTSTC dest dest code b0 b7 dsp8 0 1 1 1 1 1 1 0 0 0 0 0 DEST dsp16...
Page 178 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles BTSTS (1) BTSTS dest dest code b0 b7 0 1 1 1 1 1 1 0 0 0 0 1 DEST dsp8 dsp16 dest dest DEST DEST bit,R0 0 0 0 0 base:8[A0] 1 0 0 0 base:8[An]...
Page 179 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (1) CMP.size:G #IMM, dest dest code b0 b7 0 1 1 1 0 1 1 SIZE 1 0 0 0 DEST dsp8 #IMM8 dsp16/abs16 #IMM16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0...
Page 180 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (2) CMP.size:Q #IMM, dest dest code b0 b7 1 1 0 1 0 0 0 SIZE IMM4 DEST dsp8 dsp16/abs16 .size SIZE #IMM IMM4 IMM4 #IMM 0 0 0 0 1 0 0 0 –8 0 0 0 1...
Page 181 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (3) CMP.B:S #IMM8, dest dest code 1 1 1 0 0 DEST #IMM8 dsp8 abs16 dest DEST 0 1 1 1 0 0 dsp:8[SB] 1 0 1 dsp:8[SB/FB] dsp:8[FB] 1 1 0 abs16 abs16 1 1 1...
Page 182 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (4) CMP.size:G src, dest src code dest code b0 b7 1 1 0 0 0 0 0 SIZE DEST dsp8 dsp8 dsp16/abs16 dsp16/abs16 .size SIZE src/dest src/dest SRC/DEST SRC/DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 183 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (5) CMP.B:S src, R0L/R0H src code dsp8 0 0 1 1 1 DEST SRC abs16 dest DEST R0L/R0H dsp:8[SB] dsp:8[SB/FB] dsp:8[FB] abs16 abs16 [ Number of Bytes/Number of Cycles ] dsp:8[SB/FB] abs16 Bytes/Cycles...
Page 184 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles DADC (2) DADC.W #IMM16, R0 b0 b7 #IMM16 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 0 [ Number of Bytes/Number of Cycles ] Bytes/Cycles DADC (3) DADC.B R0H, R0L...
Page 185 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles DADC (4) DADC.W R1, R0 b0 b7 0 1 1 1 1 1 0 1 1 1 1 0 0 1 1 0 [ Number of Bytes/Number of Cycles ] Bytes/Cycles DADD (1) DADD.B #IMM8, R0L...
Page 186 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles DADD (2) DADD.W #IMM16, R0 b0 b7 #IMM16 0 1 1 1 1 1 0 1 1 1 1 0 1 1 0 0 [ Number of Bytes/Number of Cycles ] Bytes/Cycles DADD (3) DADD.B R0H, R0L...
Page 187 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles DADD (4) DADD.W R1, R0 b0 b7 0 1 1 1 1 1 0 1 1 1 1 0 0 1 0 0 [ Number of Bytes/Number of Cycles ] Bytes/Cycles (1) DEC.B dest...
Page 188 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (2) DEC.W dest 1 1 1 1 DEST 0 1 0 dest DEST [ Number of Bytes/Number of Cycles ] Bytes/Cycles (1) DIV.size #IMM b0 b7 #IMM8 0 1 1 1 1 1 0 SIZE 1 1 1 0 0 0 0 1 #IMM16 .size SIZE...
Page 189 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (2) DIV.size src src code b0 b7 dsp8 0 1 1 1 0 1 1 SIZE 1 1 0 1 dsp16/abs16 .size SIZE R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0 dsp:8[An] R0H/R1 0 0 0 1...
Page 190 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles DIVU (2) DIVU.size src src code b0 b7 dsp8 0 1 1 1 0 1 1 SIZE 1 1 dsp16/abs16 .size SIZE R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0 dsp:8[An] R0H/R1 0 0 0 1...
Page 191 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles DIVX (2) DIVX.size src src code b0 b7 dsp8 0 1 1 1 0 1 1 SIZE 1 0 0 1 dsp16/abs16 .size SIZE R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0 dsp:8[An] R0H/R1...
Page 192 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles DSBB (2) DSBB.W #IMM16, R0 b0 b7 #IMM16 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 [ Number of Bytes/Number of Cycles ] Bytes/Cycles DSBB (3) DSBB.B R0H, R0L...
Page 193 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles DSBB (4) DSBB.W R1, R0 b0 b7 0 1 1 1 1 1 0 1 1 1 1 0 0 1 1 1 [ Number of Bytes/Number of Cycles ] Bytes/Cycles DSUB (1) DSUB.B #IMM8, R0L...
Page 194 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles DSUB (2) DSUB.W #IMM16, R0 b0 b7 #IMM16 0 1 1 1 1 1 0 1 1 1 1 0 1 1 0 1 [ Number of Bytes/Number of Cycles ] Bytes/Cycles DSUB (3) DSUB.B R0H, R0L...
Page 195 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles DSUB (4) DSUB.W R1, R0 b0 b7 0 1 1 1 1 1 0 1 1 1 1 0 0 1 0 1 [ Number of Bytes/Number of Cycles ] Bytes/Cycles ENTER (1) ENTER...
Page 196 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles EXITD (1) EXITD b0 b7 0 1 1 1 1 1 0 1 1 1 1 0 0 1 0 [ Number of Bytes/Number of Cycles ] Bytes/Cycles EXTS (1) EXTS.B dest dest code b0 b7 dsp8...
Page 197 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles EXTS (2) EXTS.W R0 b0 b7 0 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 [ Number of Bytes/Number of Cycles ] Bytes/Cycles FCLR (1) FCLR dest...
Page 198 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles FSET (1) FSET dest b0 b7 1 1 1 0 1 0 1 1 0 DEST 0 1 0 0 dest DEST 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1...
Page 199 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (2) INC.W dest 1 0 1 1 DEST 0 1 0 dest DEST [ Number of Bytes/Number of Cycles ] Bytes/Cycles (1) INT #IMM #IMM 1 1 1 0 1 0 1 1 [ Number of Bytes/Number of Cycles ] Bytes/Cycles 2/19...
Page 200 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles INTO (1) INTO 1 1 1 1 0 1 1 0 [ Number of Bytes/Number of Cycles ] Bytes/Cycles • If the O flag = 1, the number of cycles indicated is increased by 19. J Cnd (1) J Cnd label...
Page 201 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles J Cnd (2) J Cnd label label code b0 b7 dsp8 0 1 1 1 1 1 0 1 1 1 0 0 dsp8 = address indicated by label – (start address of instruction + 2) 1 0 0 0 1 1 0 0 1 0 0 1...
Page 202 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (2) JMP.B label label code dsp8 1 1 1 1 1 1 1 0 dsp8 = address indicated by label – (start address of instruction + 1) [ Number of Bytes/Number of Cycles ] Bytes/Cycles (3) JMP.W label...
Page 203 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (4) JMP.A label label code abs20 1 1 1 1 1 1 0 0 [ Number of Bytes/Number of Cycles ] Bytes/Cycles JMPI (1) JMPI.W src code b0 b7 dsp8 0 1 1 1 1 1 0 1 0 0 1 0 dsp16/abs16 dsp20...
Page 204 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles JMPI (2) JMPI.A src code b0 b7 dsp8 0 1 1 1 1 1 0 1 0 0 0 0 dsp16/abs16 dsp20 0 0 0 0 dsp:8[A0] 1 0 0 0 R2R0 dsp:8[An] 0 0 0 1...
Page 205 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (1) JSR.W label label code dsp16 1 1 1 1 0 1 0 1 dsp16 = address indicated by label – (start address of instruction + 1) [ Number of Bytes/Number of Cycles ] Bytes/Cycles (2) JSR.A label...
Page 206 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles JSRI (1) JSRI.W src code b0 b7 dsp8 0 1 1 1 1 1 0 1 0 0 1 1 dsp16/abs16 dsp20 0 0 0 0 dsp:8[A0] 1 0 0 0 dsp:8[An] 0 0 0 1 dsp:8[A1]...
Page 207 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (1) LDC #IMM16, dest b0 b7 #IMM16 1 1 1 0 1 0 1 1 0 DEST 0 0 0 0 dest DEST 0 0 0 INTBL 0 0 1 INTBH 0 1 0 0 1 1...
Page 208 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles LDCTX (1) LDCTX abs16, abs20 b0 b7 abs16 abs20 0 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 [ Number of Bytes/Number of Cycles ] Bytes/Cycles 7/11+2 •...
Page 209 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (1) LDE.size abs20, dest dest code src code b0 b7 abs20 dsp8 0 1 1 1 0 1 0 SIZE 1 0 0 0 DEST dsp16/abs16 .size SIZE dest dest DEST DEST R0L/R0...
Page 210 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (3) LDE.size [A1A0], dest dest code b0 b7 dsp8 0 1 1 1 0 1 0 SIZE 1 0 1 0 DEST dsp16/abs16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 211 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles LDIPL (1) LDIPL #IMM b0 b7 0 1 1 1 1 1 0 1 1 0 1 0 #IMM [ Number of Bytes/Number of Cycles ] Bytes/Cycles (1) MOV.size:G #IMM, dest dest code b0 b7 dsp8...
Page 212 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (2) MOV.size:Q #IMM, dest dest code b0 b7 dsp8 1 1 0 1 1 0 0 SIZE IMM4 DEST dsp16/abs16 .size SIZE #IMM IMM4 IMM4 #IMM 0 0 0 0 1 0 0 0 –8 0 0 0 1...
Page 213 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (3) MOV.B:S #IMM8, dest dest code 1 1 0 0 0 DEST #IMM8 dsp8 abs16 dest DEST 0 1 1 1 0 0 dsp:8[SB] 1 0 1 dsp:8[SB/FB] dsp:8[FB] 1 1 0 abs16 abs16 1 1 1...
Page 214 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (4) MOV.size:S #IMM, dest #IMM8 1 SIZE 1 0 DEST 0 1 0 #IMM16 .size SIZE dest DEST [ Number of Bytes/Number of Cycles ] Bytes/Cycles • If the size specifier (.size) is (.W), the number of bytes and cycles indicated are increased by 1 each. (5) MOV.B:Z #0, dest dest code dsp8...
Page 215 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (6) MOV.size:G src, dest src code dest code b0 b7 dsp8 dsp8 0 1 1 1 0 0 1 SIZE DEST dsp16/abs16 dsp16/abs16 .size SIZE src/dest src/dest SRC/DEST SRC/DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 216 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (7) MOV.B:S src, dest src code 0 0 1 1 0 DEST SRC dsp8 abs16 dest DEST R0L/R0H dsp:8[SB] dsp:8[SB/FB] dsp:8[FB] abs16 abs16 [ Number of Bytes/Number of Cycles ] dsp:8[SB/FB] abs16 Bytes/Cycles...
Page 217 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (9) MOV.B:S src, R0L/R0H src code 0 0 0 0 1 DEST SRC dsp8 abs16 dest DEST R0L/R0H dsp:8[SB] dsp:8[SB/FB] dsp:8[FB] abs16 abs16 [ Number of Bytes/Number of Cycles ] dsp:8[SB/FB] abs16 Bytes/Cycles...
Page 218 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (11) MOV.size:G src, dsp:8[SP] src code dest code b0 b7 dsp8 dsp8 0 1 1 1 0 1 0 SIZE 0 0 1 1 dsp16/abs16 .size SIZE R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0 dsp:8[An]...
Page 219 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles MOV Dir (1) MOV Dir R0L, dest dest code b0 b7 dsp8 0 1 1 1 1 1 0 0 1 0 DIR DEST dsp16/abs16 dest dest DEST DEST 0 0 0 0 dsp:8[A0] 1 0 0 0 dsp:8[An]...
Page 220 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles MOV Dir (2) MOV Dir src, R0L dest code b0 b7 dsp8 0 1 1 1 1 1 0 0 0 0 DIR dsp16/abs16 0 0 0 0 dsp:8[A0] 1 0 0 0 dsp:8[An] 0 0 0 1 dsp:8[A1]...
Page 221 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (1) MUL.size #IMM, dest dest code b0 b7 dsp8 #IMM8 0 1 1 1 1 1 0 SIZE 0 1 0 1 DEST dsp16/abs16 #IMM16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0...
Page 222 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (2) MUL.size src, dest src code dest code b0 b7 dsp8 dsp8 0 1 1 1 1 0 0 SIZE DEST dsp16/abs16 dsp16/abs16 .size SIZE R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0 dsp:8[An]...
Page 223 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles MULU (1) MULU.size #IMM, dest dest code b0 b7 dsp8 #IMM8 0 1 1 1 1 1 0 SIZE 0 1 0 0 DEST dsp16/abs16 #IMM16 .size SIZE dest dest DEST DEST R0L/R0...
Page 224 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles MULU (2) MULU.size src, dest src code dest code b0 b7 dsp8 dsp8 0 1 1 1 0 0 0 SIZE DEST dsp16/abs16 dsp16/abs16 .size SIZE R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0 dsp:8[An]...
Page 225 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (1) NEG.size dest dest code b0 b7 dsp8 0 1 1 1 0 1 0 SIZE 0 1 0 1 DEST dsp16/abs16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0 dsp:8[An]...
Page 226 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (1) NOT.size:G dest dest code b0 b7 dsp8 0 1 1 1 0 1 0 SIZE 0 1 1 1 DEST dsp16/abs16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0 dsp:8[An]...
Page 227 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (1) OR.size:G #IMM, dest dest code b0 b7 dsp8 #IMM8 0 1 1 1 0 1 1 SIZE 0 0 1 1 DEST #IMM16 dsp16/abs16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0...
Page 228 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (3) OR.size:G src, dest src code dest code b0 b7 dsp8 dsp8 1 0 0 1 1 0 0 SIZE DEST dsp16/abs16 dsp16/abs16 .size SIZE src/dest src/dest SRC/DEST SRC/DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 229 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (4) OR.B:S src, R0L/R0H dest code dsp8 0 0 0 1 1 DEST SRC abs16 dest DEST R0L/R0H dsp:8[SB] dsp:8[SB/FB] dsp:8[FB] abs16 abs16 [ Number of Bytes/Number of Cycles ] dsp:8[SB/FB] abs16 Bytes/Cycles...
Page 230 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (2) POP.B:S dest 1 0 0 1 DEST 0 1 0 dest DEST [ Number of Bytes/Number of Cycles ] Bytes/Cycles (3) POP.W:S dest 1 1 0 1 DEST 0 1 0 dest DEST [ Number of Bytes/Number of Cycles ]...
Page 231 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles POPC (1) POPC dest b0 b7 1 1 1 0 1 0 1 1 0 DEST 0 0 1 1 dest DEST dest DEST 0 0 0 1 0 0 INTBL 0 0 1 1 0 1...
Page 232 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles PUSH (1) PUSH.size:G #IMM b0 b7 #IMM8 0 1 1 1 1 1 0 SIZE 1 1 1 0 0 0 1 0 #IMM16 .size SIZE [ Number of Bytes/Number of Cycles ] Bytes/Cycles •...
Page 233 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles PUSH (3) PUSH.B:S 1 0 0 0 SRC 0 1 0 [ Number of Bytes/Number of Cycles ] Bytes/Cycles PUSH (4) PUSH.W:S 1 1 0 0 SRC 0 1 0 [ Number of Bytes/Number of Cycles ] Bytes/Cycles Rev.2.00 Oct 17, 2005...
Page 234 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles PUSHA (1) PUSHA src code b0 b7 dsp8 0 1 1 1 1 1 0 1 1 0 0 1 dsp16/abs16 dsp:8[A0] 1 0 0 0 dsp:8[An] dsp:8[A1] 1 0 0 1 dsp:8[SB] 1 0 1 0 dsp:8[SB/FB]...
Page 235 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles PUSHM (1) PUSHM src 1 1 1 0 1 1 0 0 R0 R1 A0 A1 SB FB • The bit for a selected register is 1. The bit for a non-selected register is 0. [ Number of Bytes/Number of Cycles ] Bytes/Cycles 2/2 m...
Page 236 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles RMPA (1) RMPA.size b0 b7 0 1 1 1 1 1 0 SIZE 1 1 1 1 0 0 0 1 .size SIZE [ Number of Bytes/Number of Cycles ] 2/4+7 Bytes/Cycles •...
Page 237 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles RORC (1) RORC.size dest dest code b0 b7 dsp8 0 1 1 1 0 1 1 SIZE 1 0 1 1 DEST dsp16/abs16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 238 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (1) ROT.size #IMM, dest dest code b0 b7 1 1 1 0 0 0 0 SIZE IMM4 DEST dsp8 dsp16/abs16 .size SIZE #IMM IMM4 IMM4 #IMM 0 0 0 0 1 0 0 0 –1 0 0 0 1...
Page 239 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (2) ROT.size R1H, dest dest code b0 b7 dsp8 0 1 1 1 0 1 0 SIZE 0 1 1 0 DEST dsp16/abs16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 240 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (1) SBB.size #IMM, dest dest code b0 b7 dsp8 #IMM8 0 1 1 1 0 1 1 SIZE 0 1 1 1 DEST dsp16/abs16 #IMM16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0...
Page 241 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (2) SBB.size src, dest src code dest code b0 b7 1 0 1 1 1 0 0 SIZE DEST dsp8 dsp8 dsp16/abs16 dsp16/abs16 .size SIZE src/dest src/dest SRC/DEST SRC/DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 242 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles SBJNZ (1) SBJNZ.size #IMM, dest, label dest code label code b0 b7 dsp8 dsp8 1 1 1 1 1 0 0 SIZE IMM4 DEST dsp16/abs16 dsp8 (label code) = address indicated by label – (start address of instruction + 2) .size SIZE #IMM...
Page 243 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (1) SHA.size #IMM, dest dest code b0 b7 dsp8 1 1 1 1 0 0 0 SIZE IMM4 DEST dsp16/abs16 .size SIZE #IMM IMM4 IMM4 #IMM 0 0 0 0 1 0 0 0 –1 0 0 0 1...
Page 244 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (2) SHA.size R1H, dest dest code b0 b7 0 1 1 1 0 1 0 SIZE 1 1 1 1 DEST dsp8 dsp16/abs16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 245 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (4) SHA.L R1H, dest b0 b7 1 1 1 0 1 0 1 1 0 0 1 DEST 0 0 0 1 dest DEST R2R0 R3R1 [ Number of Bytes/Number of Cycles ] Bytes/Cycles 2/4+m •...
Page 246 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (1) SHL.size #IMM, dest dest code b0 b7 1 1 1 0 1 0 0 SIZE IMM4 DEST dsp8 dsp16/abs16 .size SIZE #IMM IMM4 IMM4 #IMM 0 0 0 0 1 0 0 0 –1 0 0 0 1...
Page 247 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (2) SHL.size R1H, dest dest code b0 b7 dsp8 0 1 1 1 0 1 0 SIZE 1 1 1 0 DEST dsp16/abs16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 248 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (4) SHL.L R1H, dest b0 b7 1 1 1 0 1 0 1 1 0 0 0 DEST 0 0 0 1 dest DEST R2R0 R3R1 [ Number of Bytes/Number of Cycles ] Bytes/Cycles 2/4+m •...
Page 249 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles SMOVF (1) SMOVF.size b0 b7 0 1 1 1 1 1 0 SIZE 1 1 1 0 1 0 0 0 .size SIZE [ Number of Bytes/Number of Cycles ] Bytes/Cycles 2/5+5 •...
Page 250 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (1) STC src, dest dest Code b0 b7 dsp8 0 1 1 1 1 0 1 1 1 DEST dsp16/abs16 dest DEST dest DEST 0 0 0 0 0 0 0 dsp:8[A0] 1 0 0 0 dsp:8[An]...
Page 251 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles STCTX (1) STCTX abs16, abs20 b0 b7 abs16 abs20 0 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 [ Number of Bytes/Number of Cycles ] Bytes/Cycles 7/11+2 •...
Page 252 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (2) STE.size src, dsp:20[A0] src code dest code b0 b7 dsp8 dsp20 0 1 1 1 0 1 0 SIZE 0 0 0 1 dsp16/abs16 .size SIZE R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0 dsp:8[An]...
Page 253 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles STNZ (1) STNZ #IMM8, dest dest code #IMM8 dsp8 1 1 0 1 0 DEST abs16 dest DEST 0 1 1 1 0 0 dsp:8[SB] 1 0 1 dsp:8[SB/FB] dsp:8[FB] 1 1 0 abs16 abs16...
Page 254 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles STZX (1) STZX #IMM8 , #IMM8 , dest dest code #IMM82 1 1 0 1 1 DEST dsp8 #IMM81 abs16 dest DEST 0 1 1 1 0 0 dsp:8[SB] 1 0 1 dsp:8[SB/FB] dsp:8[FB] 1 1 0...
Page 255 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (2) SUB.B:S #IMM8, dest dest code #IMM8 1 0 0 0 1 DEST dsp8 abs16 dest DEST 0 1 1 1 0 0 dsp:8[SB] 1 0 1 dsp:8[SB/FB] dsp:8[FB] 1 1 0 abs16 abs16 1 1 1...
Page 256 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (3) SUB.size:G src, dest src code dest code b0 b7 dsp8 dsp8 1 0 1 0 1 0 0 SIZE DEST dsp16/abs16 dsp16/abs16 .size SIZE src/dest src/dest SRC/DEST SRC/DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 257 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (4) SUB.B:S src, R0L/R0H dest code dsp8 0 0 1 0 1 DEST SRC abs16 dest DEST R0L/R0H dsp:8[SB] dsp:8[SB/FB] dsp:8[FB] abs16 abs16 [ Number of Bytes/Number of Cycles ] dsp:8[SB/FB] abs16 Bytes/Cycles...
Page 258 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (2) TST.size src, dest src code dest code b0 b7 1 0 0 0 0 0 0 SIZE DEST dsp8 dsp8 dsp16/abs16 dsp16/abs16 .size SIZE src/dest src/dest SRC/DEST SRC/DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 259 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (1) UND 1 1 1 1 1 1 1 1 [ Number of Bytes/Number of Cycles ] 1/20 Bytes/Cycles WAIT (1) WAIT b0 b7 0 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 [ Number of Bytes/Number of Cycles ] Bytes/Cycles Rev.2.00 Oct 17, 2005...
Page 260 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles XCHG (1) XCHG.size src, dest dest code b0 b7 dsp8 0 1 1 1 1 0 1 SIZE 0 0 SRC DEST dsp16/abs16 .size SIZE R0L/R0 R0H/R1 R1L/R2 R1H/R3 dest dest DEST DEST...
Page 261 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (1) XOR.size #IMM, dest dest code b0 b7 dsp8 #IMM8 0 1 1 1 0 1 1 SIZE 0 0 0 1 DEST dsp16/abs16 #IMM16 .size SIZE dest dest DEST DEST R0L/R0 0 0 0 0...
Page 262 Chapter 4 Instruction Codes/Number of Cycles Instruction Codes/Number of Cycles (2) XOR.size src, dest src code dest code b0 b7 dsp8 dsp8 1 0 0 0 1 0 0 SIZE DEST dsp16/abs16 dsp16/abs16 .size SIZE src/dest src/dest SRC/DEST SRC/DEST R0L/R0 0 0 0 0 dsp:8[A0] 1 0 0 0...
Page 263: Chapter 5 Interrupts
Chapter 5 Interrupts 5.1 Outline of Interrupts 5.2 Interrupt Control 5.3 Interrupt Sequence 5.4 Returning from Interrupt Routines 5.5 Interrupt Priority 5.6 Multiple Interrupts 5.7 Notes on Interrupts...
Page 264: Outline Of Interrupts
Chapter 5 Interrupts 5.1 Outline of Interrupts 5.1 Outline of Interrupts When an interrupt request is acknowledged, control branches to the interrupt routine that is set in an inter- rupt vector table. Each interrupt vector table must have had the start address of its corresponding interrupt routine set.
Page 265: Software Interrupts
Chapter 5 Interrupts 5.1 Outline of Interrupts Table 5.1.1 Interrupt Sources (Nonmaskable) and Fixed Vector Tables Vector Table Addresses Interrupt Source Description Address (L) to Address (H) Undefined Instruction 0FFDC to 0FFDF Interrupt generated by the UND instruction. Overflow 0FFE0 to 0FFE3 Interrupt generated by the INTO instruction.
Page 266: Hardware Interrupts
Chapter 5 Interrupts 5.1 Outline of Interrupt 5.1.3 Hardware Interrupts There are two types in hardware interrupts: special interrupts and peripheral function interrupts. Special interrupts Special interrupts are nonmaskable. (1) Watchdog timer interrupt This interrupt is caused by the watchdog timer. Initialize the watchdog timer after the watchdog timer interrupt is generated.
Page 267: Interrupt Control
Chapter 5 Interrupts 5.2 Interrupt Control 5.2 Interrupt Control This section explains how to enable/disable maskable interrupts and set acknowledge priority. The expla- nation here does not apply to non-maskable interrupts. Maskable interrupts are enabled and disabled by using the I flag, IPL, and bits ILVL2 to ILVL0 in each interrupt control register.
Page 268: Ilvl2 To Ilvl0 Bis, Ipl
Chapter 5 Interrupts 5.2 Interrupt Control 5.2.3 ILVL2 to ILVL0 bis, IPL Interrupt priority levels can be set using bits ILVL2 to ILVL0. Table 5.2.1 shows how interrupt priority levels are set. Table 5.2.2 shows interrupt enable levels in relation to IPL. The following lists the conditions under which an interrupt request is acknowledged: •...
Page 269: Changing Interrupt Control Register
Chapter 5 Interrupts 5.2 Interrupt Control 5.2.4 Changing Interrupt Control Registers (1) Individual interrupt control registers can only be modified while no interrupt requests corresponding to that register are generated. If interrupt requests managed by the interrupt control register are likely to occur, disable interrupts before changing the contents of the interrupt control register.
Page 270: Interrupt Sequence
Chapter 5 Interrupts 5.3 Interrupt Sequence 5.3 Interrupt Sequence The interrupt sequence — the operations performed from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed and transfers control to the interrupt sequence from the next cycle.
Page 271: Interrupt Response Time
Chapter 5 Interrupts 5.3 Interrupt Sequence 5.3.1 Interrupt Response Time Figure 5.3.2 shows the interrupt response time. The interrupt response time is the period from when an interrupt request is generated until the first instruction of the interrupt routine is executed. This period consists of the time ((a) in Figure 5.3.1) from when the interrupt request is generated to when the instruction then under way is completed and the time (20 cycles (b)) in which the interrupt sequence is executed.
Page 272: Saving Register Contents
Chapter 5 Interrupts 5.3 Interrupt Sequence 5.3.3 Saving Register Contents In an interrupt sequence, the contents of the FLG register and the PC are saved to the stack area. The order in which these are saved is as follows. First, the 4 high-order bits of the PC and 4 high-order bits (IPL) and 8 low-order bits of the FLG register, a total of 16 bits, are saved to the stack area.
Page 273: Returning From Interrupt Routines
Chapter 5 Interrupts 5.4 Returning from Interrupt Routines 5.4 Returning from Interrupt Routines When the REIT instruction is executed at the end of the interrupt routine, the contents of the FLG register and PC that have been saved to the stack area immediately preceding the interrupt sequence are automati- cally restored.
Page 274: Interrupt Priority
Chapter 5 Interrupts 5.5 Interrupt Priority 5.5 Interrupt Priority If two or more interrupt requests occur while a single instruction is being executed, the interrupt request that has higher priority is acknowledged. The priority level of maskable interrupts (peripheral functions) can be selected arbitrarily by setting bits ILVL2 to ILVL0.
Page 275: Multiple Interrupts
Chapter 5 Interrupts 5.6 Multiple interrupts 5.6 Multiple Interrupts The internal bit states when control has branched to an interrupt routine are as follows: • The interrupt enable flag (I flag) is cleared to 0 (interrupts disabled). • The interrupt request bit for the acknowledged interrupt is cleared to 0. •...
Page 276 Chapter 5 Interrupts 5.6 Multiple interrupts Interrupt request Nesting generated Reset Main routine Time I = 0 IPL = 0 Interrupt 1 I = 1 Interrupt priority level = 3 Interrupt 1 I = 0 IPL = 3 Interrupt 2 Multiple interrupts I = 1 Interrupt priority level = 5...
Page 277: Note On Interrupts
Chapter 5 Interrupts 5.7 Notes on Interrupts 5.7 Note on Interrupts 5.7.1 Reading Address 00000 Avoid reading address 00000 in a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from address 00000 during the interrupt sequence.
Page 278 Chapter 5 Interrupts Example 1: Use NOP instruction to prevent I flag being set to 1 before interrupt control register is changed INT_SWITCH1: FCLR ; Disable interrupts AND.B #00H, 0056H ; Set TXIC register to 00 FSET ; Enable interrupts Example 2: Use dummy read to delay FSET instruction INT_SWITCH2: FCLR...
Page 279: Chapter 6 Calculating The Number Of Cycles
Chapter 6 Calculating the Number of Cycles 6.1 Instruction Queue Buffer...
Page 280: Instruction Queue Buffer
6.1 Instruction Queue Buffer 6.1 Instruction Queue Buffer R8C/Tiny Series microcomputers have 4-stage (4-byte) instruction queue buffers. If the instruction queue buffer has free space when the CPU can use the bus, instruction codes are taken into the instruction queue buffer.
Page 281 Chapter 6 Calculating the Number of Cycles 6.1 Instruction Queue Buffer I n s t r u c t i o n s JMP TEST_12 JMP TEST_11 MOV.W u n d e r e x e c u t i o n F e t c h c o d e 7 3 F 1 0040...
Page 282 Q & A Information in Q&A form to help the user make the most of the R8C/Tiny Series is provided in this section. In general, one question and its corresponding answer are given on one page; the upper section is used for the question, the lower for the answer.
Page 283 How do I distinguish between the static base register (SB) and the frame base register (FB)? SB and FB function in the same manner, so you can use them as you like when in programming in assembly language. If you write a program in C, use FB as a stack frame base register. Q&A-2...
Page 284 Interrupt Is it possible to change the contents of the interrupt table register (INTB) while a program is being executed? Yes. But there is a possibility of program runaway if an interrupt request occurs while changing the contents of INTB. It is therefore not recommended to frequently change the contents of INTB while a program is being executed.
Page 285 What is the difference between the user stack pointer (USP) and the interrupt stack pointer (ISP)? What are their roles? USP is used when using the OS. When several tasks are run, the OS secures stack areas to save the contents of registers for individual tasks. Also, stack areas have to be secured, task by task, to be used for handling interrupts that occur while tasks are being executed.
Page 286 What happens to the instruction code if I use a bit instruction in absolute addressing ? This explanation takes BSET bit, base:16 as an example. This instruction is a 4-byte instruction. The 2 higher-order bytes of the instruction code indicate the operation code, and the 2 lower-order bytes make up the addressing mode to expresse bit,base:16.
Page 287 What is the difference between the DIV instruction and the DIVX instruction? The DIV instruction and the DIVX instruction are both instructions for signed division, but the sign of the remainder is different. The sign of the remainder left after the DIV instruction is the same as that of the dividend, but the sign of the remainder of the DIVX instruction is the same as that of the divisor.
Page 288 Glossary Technical terms used in this software manual are explained in this section. They apply to in this manual only. Glossary-1...
Page 289 The difference between the initial position and a later position. effective address The address actually used after modification. extension area For the R8C/Tiny Series, the area from 10000 through FFFFF Abbreviation for Least Significant Bit The bit occupying the lowest-order position in a data item.
Page 290 Term Meaning Related word macro instruction An instruction, written in a source language, to be expressed in a number of machine instructions when compiled into a machine code program. Abbreviation for Most Significant Bit. The bit occupying the highest-order position in a data item.
Page 291 Term Meaning Related word shift out To move the content of a register either to the right or left until fully overflowed. sign bit A bit that indicates either a positive or a negative (the highest-order bit). sign extension To extend a data length in which the higher-order bits to be extended are made to have the same sign as the sign bit.
Page 292 Table of Symbols The symbols used in this software manual are explained in the following table. They apply to this manual only. Symbol-1...
Page 293 Symbol Meaning Transposition from the right side to the left side Interchange between the right side and the left side Addition Subtraction Multiplication Division Logical conjunction Logical disjunction Exclusive disjunction Logical negation dsp16 16-bit displacement dsp20 20-bit displacement dsp8 8-bit displacement EVA( ) An effective address indicated by what is enclosed in ( ) EXT( )
Page 294 Index Frame base register ••• 5 Function ••• 37 A0 and A1 ••• 5 A1A0 ••• 5 Address register ••• 5 Interrupt table register ••• 5 Address space ••• 3 I flag ••• 6 Addressing mode ••• 22 Instruction code ••• 138 Instruction Format •••...
Page 295 Operation ••• 37 Overflow flag ••• 6 U flag ••• 6 User stack pointer ••• 5 USP ••• 5 PC ••• 5 Processor interrupt priority level ••• 7 Program counter ••• 5 Variable vector table ••• 20 R0, R1, R2, and R3 ••• 4 Word (16-bit) data •••...
Page 296 R8C/Tiny Series Software Manual REVISION HISTORY Rev. Date Description Page Summary 1.00 – First edition issued Jun 19, 2003 2.00 All pages Featuring improved English Oct 17, 2005 “1.1.2 Speed Performance” revised...
Page 297 R8C/Tiny Series SOFTWARE MANUAL Publication Data : Rev.1.00 Jun 19, 2003 Rev.2.00 Oct 17, 2005 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 298 R8C/Tiny Series Software Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan...

Renesas R8C/Tiny Series Software Manual

Chapter 1 Overview

Chapter 2 Addressing Modes

Chapter 3 Functions

Chapter 4 Instruction Codes/Number of Cycles

Chapter 5 Interrupts

Chapter 6 Calculating the Number of Cycles

Quick Links

Related Manuals for Renesas R8C/Tiny Series

Summary of Contents for Renesas R8C/Tiny Series

Table of Contents