Modem Status Register - Renesas EMMA Mobile 1 User Manual

Multimedia processor for mobile applications uart interface
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3.2.8 Modem status register

This register (MSR: 5000_001CH (UART0), 5001_001CH (UART1), 5002_001CH (UART2)) is used to check the
control signals connected to modems (or other peripheral devices).
15
14
7
6
DCD
RI
Name
R/W
Reserved
R
DCD *
R
RI *
R
DSR *
R
CTS *
R
DCD *
R
TERI *
R
DSR *
R
CTS *
R
* Do not poll these bits to check the interrupt source. Instead, check the source after the interrupt is detected.
CHAPTER 3 REGISTERS
13
12
Reserved
5
4
DSR
CTS
Bit
After Reset
15:8
0
Reserved. When these bits are read, 0 is returned for each bit.
7
Undefined
Indicates the inverted level of DCDZ (internal signal) input.
0: High (inactive)
In local loopback mode, the value set to bit 3 (OUT2) of the MCR
register is read.
6
Undefined
Indicates the inverted level of RIZ (internal signal) input.
0: High (inactive)
In local loopback mode, the value set to bit 2 (OUT1) of the MCR
register is read.
5
Undefined
Indicates the inverted level of DSRZ (internal signal) input.
0: High (inactive)
In local loopback mode, the value set to bit 0 (DTR : internal signal)
of the MCR register is read.
4
Undefined
Indicates the inverted level of UARTx_CTSB pin input.
0: High (inactive)
In local loopback mode, the value set to bit 1 (RTS) of the MCR
register is read.
3
Undefined
This bit is set to 1 when the level of the DCDZ (internal signal) input
changes (from high to low or low to high).
Reading this register clears this bit to "0".
2
Undefined
This bit is set to 1 when the RIZ (internal signal) input is pulled high
(inactive).
Reading this register clears this bit to "0".
1
Undefined
This bit is set to 1 when the level of the DSRZ (internal signal) input
changes (from high to low or low to high).
Reading this register clears this bit to "0".
0
Undefined
This bit is set to 1 when the level of the UARTx_CTSB pin input
changes (from high to low or low to high).
Reading this register clears this bit to "0".
User's Manual S19262EJ3V0UM
11
10
3
2
DCD
TERI
Function
1: Low (active)
1: Low (active)
1: Low (active)
1: Low (active)
9
8
1
0
DSR
CTS
27

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