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(4)
External memory area
The following areas can be used as external memory area.
(a) µPD703123, 70F3123
x0100000H to xFFFBFFFH
Access to the external memory area uses the chip select signal assigned to each memory block
(which is carried out in the CS unit set by chip area selection control registers 0 and 1 (CSC0,
CSC1)).
Furthermore, the internal ROM, internal RAM, and internal peripheral I/O areas cannot be
accessed as external memory areas.
3.4.6 External memory expansion
By setting the port n mode control register (PMCn) to control mode, an external memory device can be
connected to the external memory space using each pin of ports AL, AH, DL, CS, CT, and CM. Each
register is set by selecting control mode for each pin of these ports using PMCn (n = AL, AH, DL, CS,
CT, CM).
Furthermore, the status after reset differs as shown below in accordance with the operating mode spec-
ification set by pins MODE0 to MODE3 (please refer to Operation Modes).
(a) In the case of single-chip mode
After reset, since the internal ROM area is accessed, each pin of ports AL, AH, DL, CS, CT, and CM
enters the port mode and external devices cannot be used.
To use external memory, set the port n mode control register (PMCn).
Remark: n = AL, AH, DL, CS, CT, CM
3.4.7 Recommended use of address space
The architecture of the V850E/CA1 / ATOMIC requires that a register is utilized for address generation
when accessing operand data in the data space. Operand data access from instruction can be directly
executed at the address in this pointer register ±32 KB. However, the use of general registers as pointer
registers decreases the number of usable general registers for handling variables, but minimizes the
deterioration of address calculation performance when changing the pointer value and minimizes the
program size as well.
To enhance the efficiency of using the pointer in consideration of the memory map of the V850E/CA1 /
ATOMIC, the following points are recommended:
(1)
Program space
Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to zero (0), and only the lower
26 bits are valid. Therefore, a contiguous 64 MB space, starting from address 00000000H, uncondi-
tionally corresponds to the memory map of the program space.
(2)
Data space
For the efficient use of resources to be performed through the wrap-around feature of the data
space, the continuous 16 MB address spaces 00000000H to 00FFFFFFH and FF000000H to
FFFFFFFFH of the 4 GB CPU address space are used as the data space. With the V850E/CA1 /
ATOMIC, 64 MB physical address space is seen as 64 images in the 4 GB CPU address space.
The highest bit (bit 25) of this 26-bit address is assigned as address sign-extended to 32 bits.
68
Chapter 3 CPU Function
Preliminary User's Manual U14913EE1V0UM00
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