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(12) Timer E software event capture registers 0 to 2 (CSCE0 to CECE2)
The CSCE0n register sets capture operation by software in the capture register mode (n = 0 to 2).
This register can be read/written in 16-bit units.
Figure 9-25: Timer E Software Event Capture Registers 0 to 2 (CSCE0 to CSCE2)
15
14
13
12
CSCE0
0
0
0
CSCE1
0
0
0
CSCE2
0
0
0
Bit Position
Bit Name
5 to 0
SEVEx
Cautions: 1. The SEVEx bit ignores the settings of the EEVEx and the LNKEx bits of the
CMSEmn register.
2. The SEVEx bit is automatically cleared (0) at the end of an event.
Remark: x = 0 to 5
n = 0 to 2
m = 12, 34, 05
280
Chapter 9 Timer / Counter (Real Time Pulse Unit)
11
10
9
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Specifies capture operation by software in capture register mode of sub-channel x of
the corresponding timer TMEn.
0: Continue normal operation.
1: Perform capture operation.
Preliminary User's Manual U14913EE1V0UM00
7
6
5
4
3
0
0
SEVE5 SEVE4 SEVE3 SEVE2 SEVE1 SEVE0 FFFFF66AH 0000H
0
0
SEVE5 SEVE4 SEVE3 SEVE2 SEVE1 SEVE0 FFFFF6AAH 0000H
0
0
SEVE5 SEVE4 SEVE3 SEVE2 SEVE1 SEVE0 FFFFF6EAH 0000H
Function
2
1
0
Address
Initial
value
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