Basic Configuration; Table 9-2: Timer E Configuration List - NEC V850E/CA1 ATOMIC Preliminary User's Manual

9.2.3 Basic configuration

The basic configuration is shown below.
Timer Count Clock
Timer f
/2,
CPU
En
f
/4,
CPU
f
/8,
CPU
f
/16,
CPU
f
/32,
CPU
f
/64,
CPU
f
/128,
CPU
TIEn pin
Notes: 1. Refer to OTMEx1, OTMEx0 bits in (5)"Timer E output control registers 0 to 2 (OCTLE0 to
OCTLE2)" on page 271
2. Reset operation by zero count signal is enabled.
3. Cascade operation with TBASE0n and TBASE1n is enabled.
4. Only in buffer-less mode (BFEEx) bit of CMSEmn register = 0)
5. Cascade operation using the CVSExn register and CVPExn register is enabled.
Remarks: 1. f : Internal system clock
CPU
2. S/R: Set/Reset
3. m = 12, 34; x = 1 to 4; n = 0 to 2)
258
Chapter 9 Timer / Counter (Real Time Pulse Unit)

Table 9-2: Timer E Configuration List

Register R/W Generated
Interrupt
Signal
TBASE0n – TINTOVE0n
TBASE1n – TINTOVE1n
CVSE0n R/W TINTCCE0n INTPE0n/
CVSE1n R/W –
CVSE2n R/W –
CVSE3n R/W –
CVSE4n R/W –
CVSE5n R/W TINTCCE5n INTPE5n/
CVPE4n R TINTCCE4n INTPE4n/
CVPE3n R TINTCCE3n INTPE3n/
CVPE2n R TINTCCE2n INTPE2n/
CVPE1n R TINTCCE1n INTPE1n/
Preliminary User's Manual U14913EE1V0UM00
Capture Trigger
Timer Output
–
–
INTPE5n
INTPE1n/
TOE1n
INTPE4n
TOE4n
INTPE2n/
TOE2n
INTPE3n
TOE3n
INTPE3n/
TOE3n
INTPE2n
TOE2n
INTPE4n/
TOE4n
INTPE1n
TOE1n
INTPE0n
TOE4n/TOE3n
INTPE1n
TOE3n/TOE2n
INTPE2n
TOE2n/TOE1n
INTPE3n
TOE1n/TOE43n
INTPE4n
Note 1 Other
Functions
S/R
Note 2 Note 3
Note 2 Note 3
– –
Note 4 Note 5
/ Buffer
Note 4
Note 4 Note 5
/ Buffer
Note 4
Note 4 Note 5
/ Buffer
Note 4
Note 4 Note 5
/ Buffer
Note 4
– –
Note 5
Note 5
Note 5
Note 5