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(8)
Timer E sub-channel 3, 4 capture/compare control registers 0 to 2 (CMSE340 to CMSE342)
The CMSE34n register controls the timer TMEn sub-channel x sub capture/compare register
(CVSExn) and the timer TMEn sub-channel x main capture/compare register (CVPExn) (x = 3, 4)
(n = 0 to 2).
This register can be read/written in 16-bit units.
Figure 9-21: Timer E Sub-Channel 3, 4 Capture/Compare Control Registers 0 to 2 (CMSE340 to
15
14
13
CMSE340
0
0 EEVE4 BFEE4 LNKE4 CCSE4 TB1E4 TB0E4 0
CMSE341
0
0 EEVE4 BFEE4 LNKE4 CCSE4 TB1E4 TB0E4 0
CMSE342
0
0 EEVE4 BFEE4 LNKE4 CCSE4 TB1E4 TB0E4 0
Bit Position Bit Name
13, 5
EEVEx
12, 4
BFEEx
Remark: x = 3, 4
n = 0 to 2
Chapter 9 Timer / Counter (Real Time Pulse Unit)
CMSE342) (1/2)
12
11
10
9
8
Enables/disables capture event detection by sub-channel x capture/compare register.
0: Don't detect events
1: Detect events
Specifies the buffer operation of sub-channel x sub capture/compare register (CVSExn).
0: Don't use sub-channel x sub capture/compare register (CVSExn) as buffer.
1: Use sub-channel x sub capture/compare register (CVSExn) as buffer.
Remarks:
1. The operations in the capture register mode and compare register mode
when the sub-channel x sub capture/compare register (CVSExn) is not
used as a buffer are shown below. (BFEEx = 0)
• In capture register mode: The CPU can read both the master register
(CVPExn) and slave register (CVSExn). The next event is ignored
until the CPU finishes reading the master register.
TME0n capture is performed by the slave register, and TME1n
capture is performed by the master register.
• In compare register mode: The CPU writes to the slave register
(CVSExn), and immediately after, the same contents as those of the
slave register are written to the master register (CVPExn).
2. The operations in the capture register mode and compare register
mode when the sub-channel x sub capture/compare register (CVSExn)
is used as a buffer are shown below. (BFEEx = 1)
• In capture register mode: When the CPU reads the master register
(CVPExn), the master register updates the value held by the slave
register (CVSExn) immediately and once only, after the CPU read
operation. When a capture event occurs, the timer counter value at
that time is always saved in the slave register.
• In compare register mode: The CPU writes to the slave register
(CVSExn) and these contents are transferred to the master register
(CVPExn) specified by the corresponding LNKEx bit.
Preliminary User's Manual U14913EE1V0UM00
7
6
5
4
3
0 EEVE3 BFEE3 LNKE3 CCSE3 TB1E3 TB0E3 FFFFF64EH 0000H
0 EEVE3 BFEE3 LNKE3 CCSE3 TB1E3 TB0E3 FFFFF68EH 0000H
0 EEVE3 BFEE3 LNKE3 CCSE3 TB1E3 TB0E3 FFFFF6CEH 0000H
Function
2
1
0
Address
Initial
value
275
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