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7.4.2 Digital Filter
Behavioral Description
The digital filter simply samples the input with the negative clock edge of the f
clock. The negative clock edge is used to suppress the sampling of glitches caused by the V850E/CA1
/ ATOMIC hardware and its external circuitry itself (assuming that all outputs from the V850E/CA1 /
ATOMIC change their values only on positive edges of the f
The digital filter's behaviour is described as follows:
The digital filter samples the input signal with its f
ognize a new value for its output, that differs from the current output state, 4 subsequent samples are
required, where each sample has read the same new input value.
However, to accept an input sample to be relevant for the new value, the level of the detection enable
signal has to be high. The detection enable signal is a divided clock derived from the system clock, with
frequencies: f
, f
CPU
CPU
To reject an input sample sequence, only one violation of an input sample against the sequence of
equal and accepted input samples is sufficient. Here, the detection enable signal is not relevant.
The following figure illustrates the behaviour of the filter's state machine.
Scan_1
first
Scan_1
second
Scan_1
third
Chapter 7 Interrupt/Exception Processing Function
/2, f
/4.
CPU
Figure 7-17: Digital Filter State Machine Diagram
RESET
Output = 0
Output = 1
Preliminary User's Manual U14913EE1V0UM00
clock or any derived sub-clock).
CPU
operating frequency (negative clock edge). To rec-
CPU
Undisturbed
sequence
Scan_0
Scan_0
second
Scan_0
internal system
CPU
input = 0 &
detect_enable = 1
input = 1 &
detect_enable = 1
input = 0
input = 1
other conditions
third
first
209
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