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The CxSYNC registers specify the data bit time (DBT), sampling point position (SPT) and synchro-
nisation jump width (SJW) of the corresponding CAN module x (x = 1 to 3).
These registers can be read/written in 8-bit and 16-bit units. However, write access is only permitted
in initialisation mode (ISTAT bit of the CxCTRL register = 1)
Figure 13-42: CAN 1 to 3 Synchronization Control Registers (C1SYNC to C3SYNC) (1/2))
15
14
13
C1SYNC
0
0
0
SAMP SJW1 SJW0 SPT4 SPT3 SPT2 SPT1 SPT0 DBT4 DBT3 DBT2 DBT1 DBT0
C2SYNC
0
0
0
SAMP SJW1 SJW0 SPT4 SPT3 SPT2 SPT1 SPT0 DBT4 DBT3 DBT2 DBT1 DBT0
C3SYNC
0
0
0
SAMP SJW1 SJW0 SPT4 SPT3 SPT2 SPT1 SPT0 DBT4 DBT3 DBT2 DBT1 DBT0
Bit Position
Bit Name
12
SAMP
11, 10
SJW1,
SJW0
9 to 5
SPT4 to
SPT0
Note: The register address is calculated according to the following formula:
effective address = PP_BASE + address offset
Chapter 13 FCAN Interface Function
12
11
10
9
8
Specifies the bit sampling.
0: Sample receive data one time at sampling point.
1: Sample receive data three times and take majority decision at sampling point.
Specifies the synchronization jump width.
SJW1
0
0
1
1
Specifies the sampling point position.
SPT4
SPT3
SPT2
0
0
0
0
0
0
0
0
0
0
1
0
Other than above
Preliminary User's Manual U14913EE1V0UM00
7
6
5
4
Function
SJW0
Synchronization Jump Width
0
1 TQ
1
2 TQ
0
3 TQ
1
4 TQ
SPT1
SPT0
0
0
0
Setting prohibited
0
0
1
0
1
0
3 TQ
0
1
1
4 TQ
1
0
0
5 TQ
·
·
·
·
·
·
0
0
0
17 TQ
Setting prohibited
Address
3
2
1
0
Offset
85EH
89EH
8DEH
Sampling Point Position
SPT = (p + 1) TQ
Initial
Note
value
0218H
0218H
0218H
p
2
3
4
·
·
·
16
443
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