NEC V850E/CA1 ATOMIC Preliminary User's Manual page 14

Figure 7-12: Interrupt Mask Registers 0 to 3 (IMR0 to IMR3) ...................................................... 205
Figure 7-13: In-Service Priority Register (ISPR) ........................................................................... 206
Figure 7-14: Maskable Interrupt Status Flag (ID) ......................................................................... 206
Figure 7-15: Timer E Input Circuit Overview ................................................................................. 207
Figure 7-16: Port Interrupt Input Circuit Overview ........................................................................ 208
Figure 7-17: Digital Filter State Machine Diagram ........................................................................ 209
Figure 7-18: Timer E Input Pin Filter Edge Detect Mode Registers
(FEM0n to FEM5n) (n=0 to 2) (1/2) ......................................................................... 210
Figure 7-19: INT0, INT1 and INT2 Input Pin Filter Edge Detect Mode Registers
(FEM03 to FEM23) ................................................................................................... 212
Figure 7-20: Software Exception Processing ................................................................................ 213
Figure 7-21: RETI Instruction Processing ..................................................................................... 214
Figure 7-22: Exception Status Flag (EP) ..................................................................................... 215
Figure 7-23: Exception Trap Processing ....................................................................................... 216
Figure 7-24: Restore Processing from Exception Trap ................................................................. 217
Figure 7-25: Debug Trap Processing ............................................................................................ 218
Figure 7-26: Restore Processing from Debug Trap ...................................................................... 219
Figure 7-27: Pipeline Operation at Interrupt Request Acknowledgment (Outline) ........................ 222
Figure 8-1: Block Diagram of the Clock Generator ..................................................................... 225
Figure 8-2: Main system clock oscillator ..................................................................................... 226
Figure 8-3: Power Save Mode State Transition Diagram ........................................................... 231
Figure 8-4: WATCH mode release by NMI or INT ...................................................................... 243
Figure 8-5: STOP mode release by NMI or INT .......................................................................... 244
Figure 8-6: WATCH mode release by reset or watchdog timer .................................................. 245
Figure 8-7: STOP mode release by RESET pin input ................................................................. 245
Figure 9-1: Block Diagram of Timer D ........................................................................................ 248
Figure 9-2: Timer D Registers 0, 1 (TMD0, TMD1) ................................................................... 249
Figure 9-3: Timer D Compare Registers 0, 1 (CMD0 to CMD1) ................................................. 250
Figure 9-4: Example of Timing During TMD Operation ............................................................... 251
Figure 9-5: Timer D Control Register 0, 1 (TMCD0 to TMCD1) ................................................. 252
Figure 9-6: TMD Compare Operation Example .......................................................................... 254
Figure 9-7: Block Diagram of Timer E ......................................................................................... 259
Figure 9-8: Timer E Time Base Counter 0 Registers 0 to 2 (TBASE00 to TBASE02) ............... 261
Figure 9-9: Timer E Time Base Counter 1 Registers 0 to 2 (TBASE10 to TBASE12) ............... 261
Figure 9-10: Timer E Sub-Channel 0 Capture/Compare Registers 0 to 2 (CVSE00 to 02) ......... 262
Figure 9-11: Timer E Sub-Channel x Main Capture/Compare Registers 0 to 2
(CVPEx0 to CVPEx2) (x = 1 to 4)
Figure 9-12: Timer E Sub-Channel x Sub Capture/Compare Registers 0 to 2
(CVSEx0 to CVSEx2) (x = 1 to 4)
Figure 9-13: Timer E Sub-Channel 5 Capture/Compare Registers (CVSE50 to CVSE52) ......... 265
Figure 9-14: Timer E Clock Stop Registers 0 to 2 (STOPTE0 to STOPTE2) .............................. 266
Figure 9-15: Timer E Count Clock/Control Edge Selection Registers 0 to 2 (CSE0 to CSE2) .... 267
Figure 9-16: Timer E Sub-Channel Input Event Edge Selection Register 0 to 2
(SESE0 to SESE2) .................................................................................................. 268
Figure 9-17: Timer E Time Base Control Registers 0 to 2 (TCRE0 to TCRE2) (1/2) ................... 269
Figure 9-18: Timer E Output Control Registers 0 to 2 (OCTLE0 to OCTLE2) .............................. 271
Figure 9-19: Timer E Sub-Channel 0, 5 Capture/Compare Control Registers 0 to 2
(CMSE050 to CMSE052) ........................................................................................ 272
Figure 9-20: Timer E Sub-Channel 1, 2 Capture/Compare Control Registers 0 to 2
(CMSE120 to CMSE122) (1/2) ................................................................................ 273
Figure 9-21: Timer E Sub-Channel 3, 4 Capture/Compare Control Registers 0 to 2
(CMSE340 to CMSE342) (1/2) ................................................................................ 275
Figure 9-22: Timer E Time Base Status Register (TBSTATE0 to TBSTATE2) ........................... 277
Figure 9-23: Timer E Capture/Compare Status Registers 0 to 2 (CCSTATE0 to CCSTATE2) ... 278
Figure 9-24: Timer E Output Delay Registers 0 to 2 (ODELE0 to ODELE2) ............................... 279
Figure 9-25: Timer E Software Event Capture Registers 0 to 2 (CSCE0 to CSCE2) .................. 280
Figure 9-26: Edge Detection Timing ............................................................................................. 281
Figure 9-27: Timer E Up Count Timing ......................................................................................... 282
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