Figure 9-39: Timer E Capture Operation: Count Value Read Timing - NEC V850E/CA1 ATOMIC Preliminary User's Manual

(4) Operation of capture/compare register (sub-channels 0, 5)
Figures 9-39 and 9-40 show the operation of the capture/compare register (sub-channels 0, 5).

Figure 9-39: Timer E Capture Operation: Count Value Read Timing

(When CMSE05n Register's CCSEx Bit = 0, EEVEx Bit = 1, and CSCEn Register's SEVEx
Bit = 0)
f
CLK
CNT 0
Note 1
LNKEx
ED1
ED2
CAPTURE_S
READ_ENABLE_S
CVSExn register Undefined
Notes: 1. LNKEx bit of CMSE05n register
2. If an event occurs in this timing, it is ignored.
Remarks: 1. f = f
CLK CPU
2. CNT:
CAPTURE_S:
ED1, ED2:
READ_ENABLE_S: Read timing for CVSExn register
3. x = 0, 5
y = 0, when x = 0
y = 1, when x = 5
n = 0 to 2
294
Chapter 9 Timer / Counter (Real Time Pulse Unit)
1 2 3
Note 2
: Base clock
Count value of time base TBASEyn
Capture trigger signal of sub capture register
Capture event signal inputs from edge selection circuit
Preliminary User's Manual U14913EE1V0UM00
4 5 6
2
7 8 9
Note 2
6
10
9