Control Registers; Figure 12-2: Asynchronous Serial Interface Mode Registers 0 To 2 (Asim0 To Asim2) (1/3) - NEC V850E/CA1 ATOMIC Preliminary User's Manual

32-/16-bit single-chip microcontroller
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12.2.3 Control registers

(1)
Asynchronous serial interface mode registers 0 to 2 (ASIM0 to ASIM2)
The ASIMn register is an 8-bit register that controls the UARTn transfer operation.
This register can be read/written in 8 bit or 1-bit units (n = 0 to 2).

Figure 12-2: Asynchronous Serial Interface Mode Registers 0 to 2 (ASIM0 to ASIM2) (1/3)

7
6
ASIM0
CAE
TXE
7
6
ASIM1
CAE
TXE
7
6
ASIM2
CAE
TXE
Bit Position
Bit Name
7
CAE
6
TXE
Chapter 12 Serial Interface Function
5
4
RXE
PS1
5
4
RXE
PS1
5
4
RXE
PS1
Function
Enables/disables clock operation.
0: Disable clock operation (reset internal circuit asynchronously.)
1: Enable clock operation
UARTn operation clock control and asynchronous reset of the internal cir-
cuit are performed with the CAE bit. When the CAE bit is set to 0, the
UARTn operation clock stops (fixed to low level), and an asynchronous
reset is applied to internal UARTn latch.
The TXDn pin output is low level when the CAE bit = 0, and high level when
the CAE bit = 1. Therefore, perform CAE setting in combination with port
mode register (PM1, PM2, PM6) so as to avoid malfunction on the other
side at start-up (Set the port to the output mode after setting the CAE bit to
1).
Input from the RXDn pin is fixed to high level with CAE bit = 0.
Enables/disables transfer.
0: Disable transfer (Perform synchronized reset of transfer circuit.)
1: Enable transfer
Cautions: 1. Set the TXE bit to 1 after setting the CAE bit to 1 when
starting transfer. Set the CAE bit to 0 after setting the
TXE bit to 0 when stopping transfer.
2. To initialize the transfer unit, clear (0) the TXE bit, and
after letting 2 Clock cycles (base clock) elapse, set (1)
the TXE bit again. If the TXE bit is not set again, initial-
ization may not be successful. (For details about the
base clock, refer to 12.2.6 Dedicated baud rate genera-
tors (BRG) of UARTn (n = 0 to 2).)
Preliminary User's Manual U14913EE1V0UM00
3
2
1
PS0
CL
SL
3
2
1
PS0
CL
SL
3
2
1
PS0
CL
SL
0
Address
ISRM
FFFFFA00H
0
Address
ISRM
FFFFFA10H
0
Address
ISRM
FFFFFA20H
Initial
value
01H
Initial
value
01H
Initial
value
01H
313

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