Configuration; Figure 6-1: Block Diagram Of Dma Controller Configuration - NEC V850E/CA1 ATOMIC Preliminary User's Manual

6.2 Configuration

Figure 6-1: Block Diagram of DMA Controller Configuration

CPU
Remark: n = 0 to 3
164
Chapter 6 DMA Functions (DMA Controller)
Internal RAM
Internal bus
On-chip peripheral I/O bus
Data Address
control control
Count
control
Channel
control
Bus interface
Preliminary User's Manual U14913EE1V0UM00
On-chip
peripheral I/O
DMA source address
register (DSAHn/DSALn)
DMA destination address
register (DDAHn/DDALn)
DMA transfer count
register (DBCn)
DMA channel control
register (DCHCn)
DMA addressing control
register (DADCn)
DMA disable status
register (DDIS)
DMA restart register (DRST)
DMA trigger factor
register (DTFRn)
DMAC
BBR
V850E/CA1