Figure 13-34: Can 1 To 3 Control Registers (C1Ctrl To C3Ctrl) (1/4) - NEC V850E/CA1 ATOMIC Preliminary User's Manual

(2) CAN 1 to 3 control registers (C1CTRL to C3CTRL)
The CxCTRL registers control the operating modes and indicate the operating status of the corre-
sponding CAN module x (x = 1 to 3).
These registers can be read in 8-bit and 16-bit units. It can be written in 16-bit units only. For setting
and clearing certain bits a special set/clear method applies (refer to chapter 13.3.1).

Figure 13-34: CAN 1 to 3 Control Registers (C1CTRL to C3CTRL) (1/4)

Read 15 14 13
C1CTRL TECS1 TECS0 RECS1 RECS0 BOFF TSTAT RSTAT ISTAT
C2CTRL TECS1 TECS0 RECS1 RECS0 BOFF TSTAT RSTAT ISTAT
C3CTRL TECS1 TECS0 RECS1 RECS0 BOFF TSTAT RSTAT ISTAT
Write 15 14 13
ST_ ST_
C1CTRL 0
DLEVT DLEVT OVM
ST_ ST_
C2CTRL 0
DLEVT DLEVT OVM
ST_ ST_
C3CTRL 0
DLEVT DLEVT OVM
Read (1/3)
Bit Position Bit Name
15, 14 TECS1,
TECS0
13, 12 RECS1,
RECS0
Note: The register address is calculated according to the following formula:
effective address = PP_BASE + address offset
Chapter 13 FCAN Interface Function
12 11 10 9 8
12 11 10 9 8
ST_ ST_ ST_ ST_ ST_
TMR STOP SLEEP INIT
ST_ ST_ ST_ ST_ ST_
TMR STOP SLEEP INIT
ST_ ST_ ST_ ST_ ST_
TMR STOP SLEEP INIT
Indicates the transmission error counter status.
TECS1 TECS0 Transmission Error Counter Status
0 0
0 1
1 0
1 1
Indicates the reception error counter status.
RECS1 RECS0 Reception Error Counter Status
0 0
0 1
1 0
1 1
Preliminary User's Manual U14913EE1V0UM00
7 6 5 4
0 DLEVR DLEVT OVM TMR STOP SLEEP INIT
0 DLEVR DLEVT OVM TMR STOP SLEEP INIT
0 DLEVR DLEVT OVM TMR STOP SLEEP INIT
7 6 5 4
CL_ CL_ CL_ CL_
0
DLEVR DLEVT OVM TMR
CL_ CL_ CL_ CL_
0
DLEVR DLEVT OVM TMR
CL_ CL_ CL_ CL_
0
DLEVR DLEVT OVM TMR
Function
Transmission error counter below warning level (< 96)
Transmission error counter in warning level range (96 to 127)
Reserved (not possible)
Transmission error counter above warning level (≥ 128)
Reception error counter below warning level (< 96)
Reception error counter in warning level range (96 to 127)
Reserved (not possible)
Reception error counter above warning level (≥ 128)
Address
3 2 1 0 Offset
850H
890H
8D0H
3 2 1 0
CL_ CL_ CL_
850H
STOP SLEEP INIT
CL_ CL_ CL_
890H
STOP SLEEP INIT
CL_ CL_ CL_
8D0H
STOP SLEEP INIT
Initial
Note value
0101H
0101H
0101H
427