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1.1 General
The V850E/CA1 / ATOMIC single chip microcontroller, is a member of NEC's V850 32-bit RISC family,
which match the performance gains attainable with RISC-based controllers to the needs of embedded
control applications. The V850 CPU offers easy pipeline handling and programming, resulting in com-
pact code size comparable to 16-bit CISC CPUs.
The V850E/CA1 / ATOMIC offers an excellent combination of general purpose peripheral functions, like
serial communication interfaces (UART, clocked SI), display drivers and measurement inputs (A/D con-
verter), with dedicated CAN network support. To support more than one CAN network, three CAN inter-
faces and a CAN gateway are implemented on chip. The CAN gateway - realised in hardware - acts as
a configurable message handler and supports the increasing demand of messages without unneces-
sarily decreasing the CPU performance.
The device offers power-saving modes to manage the power consumption effectively under varying
conditions.
(1)
V850E CPU
The V850E CPU supports the RISC instruction set, and through the use of basic instructions that can
each be executed in 1-clock period and an optimized pipeline, achieves marked improvements in
instruction execution speed. In addition, in order to make it ideal for use in digital servo control, a 32-bit
hardware multiplier enables this CPU to support multiply instructions, saturated multiply instructions, bit
operation instructions, etc.
Also, through 2-byte basic instructions and instructions compatible with high level languages, etc.,
object code efficiency in a C compiler is increased, and program size can be made more compact.
Further, since the on-chip interrupt controller provides high speed interrupt response, including
processing, this device is suited for high level real time control fields.
(2)
External memory interface function
The V850E/CA1 contains a non multiplexed external bus interface, including an address bus (24 bits)
and data bus (selectable 8 bits or 16 bits). SRAM and ROM can be connected as well as page ROM
memories.
The DMA controller allows, data transfers between internal RAM and peripheral I/O. This reduces the
CPU load.
(3)
On-chip flash memory (µPD70F3123)
The on-chip flash memory version (µPD70F3123) has on-chip an high speed flash memory, which is
able to fetch one instruction one clock cycle. It is possible to program the user application direct in the
target application, on which the V850E/CA1 is mounted. In such case system development time can be
reduced and system maintainability after shipping can be markedly improved.
(4)
A full range of development environment products
A development environment system that includes an optimized C compiler, debugger, in-circuit emula-
tor, simulator, system performance analyzer, and other elements is also available.
Chapter 1 Introduction
Preliminary User's Manual U14913EE1V0UM00
21
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