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(3)
Timer E sub-channel x main capture/compare registers 0 to 2 (CVPEx0 to CVPEx2)
(x = 1 to 4)
The CVPExn register is a 16-bit sub-channel x main capture/compare register of timer TMEn
(x = 1 to 4) (n = 0 to 2).
In the capture register mode, this register captures the value of TBASE1n when the BFEEx bit of
the CMSEmn register is zero (m = 12, 34). When the BFEEx bit = 1, this register holds the value of
TBASE0n or TBASE1n.
If the capture register mode is selected in the 32-bit mode (value of TB1Ex, TB0Ex bits of CMSEmn
register = 11B), this register captures the contents of TBASE1n (higher 16 bits).
This register is read-only in 16-bit units.
In compare mode, this register represents the actual compare value. To write a compare value, the
registers CVSExn have to be used. This double register structure refers to the buffered operations
in compare mode.
Figure 9-11: Timer E Sub-Channel x Main Capture/Compare Registers 0 to 2 (CVPEx0 to
15
14
13
CVPE10
CVPE11
CVPE12
15
14
13
CVPE20
CVPE21
CVPE22
15
14
13
CVPE30
CVPE31
CVPE32
15
14
13
CVPE40
CVPE41
CVPE42
Chapter 9 Timer / Counter (Real Time Pulse Unit)
CVPEx2) (x = 1 to 4)
12
11
10
9
8
12
11
10
9
8
12
11
10
9
8
12
11
10
9
8
Preliminary User's Manual U14913EE1V0UM00
7
6
5
4
3
7
6
5
4
3
7
6
5
4
3
7
6
5
4
3
2
1
0
Address
FFFFF652H 0000H
FFFFF692H 0000H
FFFFF6D2H 0000H
2
1
0
Address
FFFFF656H 0000H
FFFFF696H 0000H
FFFFF6D6H 0000H
2
1
0
Address
FFFFF65AH 0000H
FFFFF69AH 0000H
FFFFF6DAH
2
1
0
Address
FFFFF65EH 0000H
FFFFF69EH 0000H
FFFFF6DEH 0000H
Initial
value
Initial
value
Initial
value
Initial
value
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