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Figure 13-22: CAN Global Interrupt Pending Register (CGINTP) (2/2)
Write
Bit Position
Bit Name
7
CL_GINT7 Clears the interrupt pending bit GINT7.
3
CL_GINT3 Clears the interrupt pending bit GINT3.
2
CL_GINT2 Clears the interrupt pending bit GINT2.
1
CL_GINT1 Clears the interrupt pending bit GINT1.
Remarks: 1. The interrupts GINT1, GINT2 and GINT7 are only generated when the corresponding
interrupt enable bit in the CGIE register is set.
2. In the CGIE register is no interrupt enable bit implemented for GINT3. Thus this interrupt
cannot be disabled.
3. The interrupt pending bits must be cleared by software in the interrupt service routine.
Caution: In case the interrupt pending bit is not cleared by software in the interrupt service
routine, no subsequent interrupt is generated anymore.
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Chapter 13 FCAN Interface Function
0: No change of GINT7 bit.
1: GINT7 bit is cleared (0).
0: No change of GINT3 bit.
1: GINT3 bit is cleared (0).
0: No change of GINT2 bit.
1: GINT2 bit is cleared (0).
0: No change of GINT1 bit.
1: GINT1 bit is cleared (0).
Preliminary User's Manual U14913EE1V0UM00
Function
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