NEC V850E/CA1 ATOMIC Preliminary User's Manual page 270

Figure 9-17: Timer E Time Base Control Registers 0 to 2 (TCRE0 to TCRE2) (2/2)
Bit Position Bit Name
11, 3 ECEEy
10, 2 OSTEy
9, 8, 1, 0 UDSEy1,
UDSEy0
Cautions: 1. If there is no external count clock, when this is selected by the prescaler setting,
clear operations (external or by software) of the timebase counter does not work.
2. When clearing is performed with the ECLR signal, the TBASEyn counter is cleared
with a delay of (1 internal count clock set with bits CSEy2 to CSEy0 of the CSEn
register) + 2 base clocks. Therefore, if external clock input is selected as the inter-
nal count clock, the counter is not cleared until the external clock (TIEn) is input.
3. The ECREy bit and the ECEEy bit must not be set to 1 at the same time.
4. If either ECEEy bit or ECREy bit is set to 1, up-/down operation with external con-
trol via ECLR signal cannot be performed (UDSEy1, UDSEy0 = 10B).
5. When UDSEy1, UDSEy0 = 01B and OSTEy = 1, the counter does not count up when
the counter value is "0". Therefore, when the counter value is "0", set OSTEy = 0,
and after the value of the counter ceases to be "0", set OSTEy = 1.
6. If there is no external count clock, when this is selected by the prescaler setting,
clear operations (external or by software) of the timebase counter does not work.
Remark: y = 0, 1
n = 0 to 2
270
Chapter 9 Timer / Counter (Real Time Pulse Unit)
Specifies TBASEyn count operation enable/disable through ECLR signal input.
0: Don't enable TBASEyn count operation
1: Enable TBASEyn count operation
Cautions: 1. In the 32-bit cascade operation mode (CASE1 bit = 1), control of
the TBASEyn count operation using ECLR signal input is not
enabled.
2. When the ECEEy bit = 1, always set the CESE1 and CESE0 bits of
the CSEn register to 10B (through input).
Specifies stop mode.
0: Don't stop TBASEyn count when count value is 0.
1: Stop TBASEyn count when count value is 0.
Caution: When TBASEyn count stop is cancelled when the OSTE1y bit = 1
(TBASEyn count is stopped when the count value is 0), TBASEyn
counts up except when the UDSEy1, UDSEy0 bits = 10B. The count
direction when the UDSEy1, UDSEy0 bits = 10B is determined by the
value of the ECLR signal input.
Specifies TBASEyn up/down count.
UDSEy1 UDSEy0
0 0
0 1
1 0
1 1
Cautions: 1. In the 32-bit cascade operation mode (CASE1 bit = 1), set the
UDSEy1, UDSEy0 bits to 00B.
2. When the UDSEy1, UDSEy0 bits = 10B, be sure to set the CESE1,
CESE0 bits of the CSE0n register to 10B (through input).
3. When the UDSEy1, UDSEy0 bits = 10B, compare match between
TBASEyn and CVSEmn has no effect on the TBASEyn count
operation (m: 0 when y = 0, 5 when y = 1).
Preliminary User's Manual U14913EE1V0UM00
Function
Perform only up count.
Clear TBASEyn with compare match signal.
Count up after TBASEyn has become "0", and count down
after a compare match occurs for sub-channels 0, 5 (trian-
gular wave up/down count).
Selects up/down count according to the ECLR signal input.
Up count when ECLR = 1
Down count when ECLR = 0
Setting prohibited
Count