NEC V850E/CA1 ATOMIC Preliminary User's Manual page 13

Figure 1-1: Pin configuration of the µPD70(F)3123 microcontroller .............................................. 24
Figure 1-2: Block diagram of the µPD70(F)3123 microcontroller .................................................. 26
Figure 2-1: Pin I/O Circuits ........................................................................................................... 51
Figure 3-1: CPU Register Set ....................................................................................................... 54
Figure 3-2: Program Counter (PC) ............................................................................................... 55
Figure 3-3: Interrupt Source Register (ECR) ................................................................................ 56
Figure 3-4: Program Status Word (PSW) ..................................................................................... 57
Figure 3-5: CPU Address Space .................................................................................................. 60
Figure 3-6: Image on Address Space ........................................................................................... 61
Figure 3-7: Wrap-around of Program Space ................................................................................ 62
Figure 3-8: Wrap-around of Data Space ....................................................................................... 62
Figure 3-9: Memory Map (µPD703123, 703F123) ........................................................................ 63
Figure 3-10: Internal RAM Area ...................................................................................................... 67
Figure 3-11: Internal Peripheral I/O Area ........................................................................................ 67
Figure 3-12: Example Application of wrap-around (µPD703123) ................................................... 69
Figure 3-13: Recommended Memory Map ..................................................................................... 70
Figure 3-14: Programmable Peripheral I/O Register (Outline) ........................................................ 81
Figure 3-15: Peripheral Area Selection Control Register (BPC) ..................................................... 82
Figure 4-1: Memory Block Function ............................................................................................ 120
Figure 4-2: Chip Area Select Control Registers 0, 1 (1/2) .......................................................... 121
Figure 4-3: Big Endian Addresses within Word .......................................................................... 125
Figure 4-4: Little Endian Addresses within Word ........................................................................ 125
Figure 4-5: Example of Wait Insertion ........................................................................................ 140
Figure 5-1: Example of Connection to SRAM ............................................................................. 146
Figure 5-2: SRAM, External ROM, External I/O Access Timing (1/6) ......................................... 147
Figure 5-3: Example of Page ROM Connections ........................................................................ 154
Figure 5-4: On-Page/Off-Page Judgment during Page ROM Connection (1/2) .......................... 155
Figure 5-5: Page ROM Configuration Register (PRC) ............................................................... 157
Figure 5-6: Page ROM Access Timing (1/4) ............................................................................... 158
Figure 6-1: Block Diagram of DMA Controller Configuration ...................................................... 164
Figure 6-2: DMA Source Address Registers H0 to H3 (DSAH0 to DSAH3) ............................... 165
Figure 6-3: DMA Source Address Registers L0 to L3 (DSAL0 to DSAL3) .................................. 166
Figure 6-4: DMA Destination Address Registers 0H to 3H (DDA0H to DDA3H) ........................ 167
Figure 6-5: DMA Destination Address Registers L0 to L3 (DDAL0 to DDAL3) ........................... 168
Figure 6-6: DMA Transfer Count Registers 0 to 3 (DBC0 to DBC3) ........................................... 169
Figure 6-7: DMA Addressing Control Registers 0 to 3 (DADC0 to DADC3) ............................... 170
Figure 6-8: DMA Channel Control Registers 0 to 3 (DCHC0 to DCHC3) ................................... 171
Figure 6-9: DMA Disable Status Register (DDIS) ....................................................................... 172
Figure 6-10: DMA Restart Register (DRST) ................................................................................. 172
Figure 6-11: DMA Trigger Factor Registers 0 to 3 (DTFR0 to DTFR3) (1/3) ............................... 173
Figure 6-12: DMAC Bus Cycle (Two-Cycle Transfer) State Transition ......................................... 177
Figure 6-13: Buffer Register Configuration ................................................................................... 180
Figure 6-14: Example of Forcible Interruption of DMA Transfer ................................................... 181
Figure 7-1: Processing Configuration of Non-Maskable Interrupt ............................................... 188
Figure 7-2: Acknowledging Non-Maskable Interrupt Request .................................................... 189
Figure 7-3: Example of Non-Maskable Interrupt Request Acknowledgement Operation (1/2) ... 190
Figure 7-4: RETI Instruction Processing ..................................................................................... 192
Figure 7-5: Non-maskable Interrupt Status Flag (NP) ................................................................ 193
Figure 7-6: Voltage Comparator Mode Register (VCMPM) ........................................................ 194
Figure 7-7: Maskable Interrupt Processing ................................................................................. 196
Figure 7-8: RETI Instruction Processing ..................................................................................... 197
Figure 7-9: Example of Processing in Which Another Interrupt Request Is Issued
While an Interrupt Is Being Processed (1/2) ............................................................. 199
Figure 7-10: Example of Processing Interrupt Requests Simultaneously Generated ................... 201
Figure 7-11: Interrupt Control Register (PICn) .............................................................................. 202
List of Figures
Preliminary User's Manual U14913EE1V0UM00 13