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(f) Page ROM access timing
SBUSCLK (output)
SCSZ0-SCSZ3
(output)
SA0-SA20 (output)
SWRZ0-SWRZ1,
SWRSTBZ
(output)
SRDZ (output)
SD0-SD15
(I/O)
SWAITZ (input)
SBCYSTZ (output)
Remarks 1.
Timing when the number of waits inserted by the DWC0 or DWC1 register is 0, the
number of idle states inserted by the BCC register is 1, and the number of waits inserted
by the ASC register is 1.
2.
Broken lines indicate high impedance.
38
CHAPTER 1 PRODUCT SPECIFCATIONS
Figure 1-18. Page ROM Access Timing
TASW
T1
TDW
< t
>
DKA
< t
>
DKA
< t
>
DKWRH
< t
>
< t
>
DKRD H
DKR DL
< t
>
HKW
< t
>
SKW
< t
>
< t
>
DKBSL
DKBSH
User's Manual A19069EJ2V0UM
TW
T2
TO1
TPRW
< t
>
DKA
< t
>
HKID
< t
>
SKID
< t
>
< t
HKW
HKW
< t
>
< t
>
SKW
SKW
TW
TO2
< t
< t
< t
DKRDH
< t
>
SKID
>
< t
>
HKW
< t
>
SKW
>
DKA
>
DKA
>
< t
>
HKID
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