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1.7.6 SiP internal-connection DMA interface pins
(1) SBUSCLK-synchronization signal
The second DMA transfer request disable timing in single transfer is described below.
Parameter
SDMARQZ0-SDMARQZ3 setup time (from SBUSCLK ↑ )
SDMARQZ0-SDMARQZ3 hold time 1
SDMARQZ0-SDMARQZ3 hold time 2 (from SBUSCLK ↑ )
SDMAAKZ0-SDMAAKZ3 output delay time (from SBUSCLK ↑ ) t
SDMAAKZ0-SDMAAKZ3 low level width
STCZ0-STCZ3 output delay time (from SBUSCLK ↑ )
Remarks 1.
t
: SBUSCLK cycle
BCLK
m = 0 to 15 (DMARQZ0 to DMARQZ3 signal mask widths set via DMAIFC0 to DMAIFC3 registers)
2.
3.
n = 1 to 16 (DMAAKZ0 to DMAAKZ3 signal active-level widths set via DMAIFC0 to DMAIFC3 registers)
Figure 1-21. DMA Interface (SBUSCLK-synchronization Signal)
SBUSCLK (output)
SDMARQZn (input)
SDMAAKZn (output)
STCZn (output)
Remark
n = 0, 1
42
CHAPTER 1 PRODUCT SPECIFCATIONS
Table 1-18. SBUSCLK-synchronization Signal
< t
>
HKDR1
< t
>
SDRK
< t
DKDA
User's Manual A19069EJ2V0UM
Symbol
MIN.
t
4.3
SDRK
To DMAAKZ ↓
t
HKDR1
− 4.3
t
HKDR2
2.0
DKDA
t
− 9.0 + n × t
WDAL
BCLK
t
2.0
DKTC
< t
>
WDAL
>
< t
DKTC
MAX.
−
−
m × t
− 4.3
BCLK
11.0
9.0 + n × t
BCLK
11.0
< t
>
HKDR2
>
Unit
ns
ns
ns
ns
ns
ns
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