Dma Interface Pins - Renesas PFESiP/V850EP1 User Manual

1.7.5 DMA interface pins

(3) BUSCLK-synchronization signal
The second DMA transfer request disable timing in single transfer is described below.
Parameter
DMARQZ0-DMARQZ3 setup time(from BUSCLK ↑ )
DMARQZ0-DMARQZ3 hold time 1
DMARQZ0-DMARQZ3 hold time 2 (from BUSCLK ↑ )
DMAAKZ0-DMAAKZ3 output delay time (from BUSCLK ↑ )
DMAAKZ0-DMAAKZ3 low level width
TCZ0-TCZ3 output delay time (from BUSCLK ↑ )
Remarks 1. t BUSCLK cycle
:
BCLK
m = 0 to 15 (DMARQZ0 to DMARQZ3 signal mask widths set via DMAIFC0 to DMAIFC3 registers)
2.
3. n = 1 to 16 (DMAAKZ0 to DMAAKZ3 signal active-level widths set via DMAIFC0 to DMAIFC3 registers)
Figure 1-20. DMA Interface (BUSCLK-synchronization Signal)
BUSCLK (output)
DMARQZn (input)
DMAAKZn (output)
TCZn (output)
n = 0-3
Remark
CHAPTER 1 PRODUCT SPECIFCATIONS
Table 1-17. BUSCLK-synchronization Signal
t
SDRK
t
HKDR1
t
HKDR2
t
DKDA
t
WDAL
t
DKTC
< t >
HKDR1
< t >
SDRK
< t
DKDA
User's Manual A19069EJ2V0UM
Symbol MIN.
4.3
To DMAAKZ ↓
− 4.3
2.0
− 9.0 + n × t
BCLK
2.0
< t >
WDAL
>
< t
DKTC
MAX.
−
−
m × t − 4.3
BCLK
11.0
9.0 + n × t
BCLK
11.0
< t >
HKDR2
>
Unit
ns
ns
ns
ns
ns
ns
41