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(a) Access timing (SRAM, external ROM, external I/O)
Figure 1-3. Access Timing (SRAM, External ROM, External I/O)
BUSCLK (output)
A0-A25, CSZ0-CSZ7 (output)
BCYSTZ (output)
RDZ, IORDZ (output)
WRZ0-WRZ3, WRSTBZ, IOWRZ
(output) (write)
D0-D31 (I/O)
D0-D31 (I/O)
WAITZ (input)
Remarks 1. Timing when the number of waits set by the DWC0 and DWC1 registers is 0.
2. Broken lines indicate high impedance.
20
CHAPTER 1 PRODUCT SPECIFCATIONS
< t
>
DKA
<t
>
DKBSL
<t
>
DKRDH
(read)
< t
>
DKWRH
< t
>
HKOD
(read)
< t
>
DKOD
(write)
< t
>
SKW
User's Manual A19069EJ2V0UM
T1
TW
<t
>
DKBSH
<t
>
DKRDL
< t
>
DKWRL
< t
SKID
< t
>
< t
>
HKW
HKW
< t
T2
< t
>
DKA
< t
>
DKBSL
< t
DKRDL
< t
>
DKRDH
< t
>
< t
>
DKWR H
DKWRL
< t
>
HKID
>
< t
>
HKOD
>
SKW
>
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