Ssmdl0 To Ssmdl1 (Modulation Frequency Range) (Input); Ssadj0 To Ssadj2 (Dither Range / Mode) (Input) - Renesas PFESiP/V850EP1 User Manual

2.3.2 SSMDL0 to SSMDL1 (modulation frequency range) (input)

Set SSCG-output modulation period.
These pins are directly connected to MDL0 and MDL1 of AAPLSCGH.
Table 2-2. Setting SSCG-output Modulation Period by SSMDL0 to SSMDL1
PLL13
SSMDL1
0
0
1
1

2.3.3 SSADJ0 to SSADJ2 (dither range / mode) (input)

Set SSCG-output frequency modulation rate.
These pins are connected to ADJ0 to ADJ2 of AAPLSCGH.
If SSADJ2 = 1 and SSADJ1 = 1, the mode with no frequency modulation occurs.
Table 2-3. Setting SSCG-output Frequency Modulation Rate
PLL16
SSADJ2
0
0
0
0
1
1
1
1
Caution Setting modulation affects the UART baud rate and timer interval time.
For example, with UART, evaluate the permissible baud rate error with the other party of
communication.
CHAPTER 2 INTERNAL SSCG-PLL CHARACTERISTICS
PLL12
SSMDL0
0 15.00 to 26.25 (open)
1 25.00 to 36.75
0 35.00 to 48.30
1 45.00 to 68.25
PLL15 PLL14
SSADJ1 SSADJ0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
User's Manual A19069EJ2V0UM
Modulation Period [kHz]
Frequency Modulation Rate
Approx. − 0.5 %
Approx. − 1.0 %
Approx. − 2.0 %
Approx. − 3.0 %
Approx. − 4.0 %
Approx. − 5.0 %
No modulation
No modulation
55