Table of Contents
Advertisement
CHAPTER 2
The SSCG-PLL incorporated in PFESiP/V850EP1 is a spread spectrum clock generator used to suppress noise,
and is effective in reducing the peak value of electromagnetic interference (EMI) noise.
2.1 Block Diagram
XT1 (input)
XT2 (−)
PLL0-PLL6 (input)
PLL7-PLL9 (input)
PLL10-PLL11 (input)
PLL17-PLL18 (input)
PLL12-PLL13 (input)
PLL14-PLL16 (input)
INTERNAL SSCG-PLL CHARACTERISTICS
Figure 2-1. SSCG-PLL Block Diagram
Standby
Control
Circuit
Oscillator
M
Block
Divider
M0-M6
N0-N2
P0-P1
S0-S1
Decoder
SSMDL0-SSMDL1
SSADJ0-SSADJ2
TEST
MODE
Circuit
User's Manual A19069EJ2V0UM
Charge
PFD
Pump
+LFP
Modulation Block
PC
P
VCO
FO (output)
Divider
51
Advertisement
Table of Contents
