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<R>
(2) Output clock
Parameter
BUSCLK output cycle
BUSCLK high-level width
BUSCLK low-level width
BUSCLK rise time
BUSCLK fall time
SBUSCLK high-level width
SBUSCLK low-level width
SBUSCLK rise time
SBUSCLK fall time
VBCLKOUT output cycle
PLLFO output cycle
CHAPTER 1 PRODUCT SPECIFCATIONS
Table 1-9. Output Clock Timing
Symbol
t
Output load capacitance: 30 pF and less
BCYC
t
WKH1
t
WKL1
t
KR1
t
KF1
t
WSKH1
t
WSKL1
t
SKR1
t
SKF1
t
Output load capacitance: 30 pF and less
VCYC
t
Output load capacitance: 20 pF and less
PLCYC
Figure 1-1. Output Clock Timing
BUSCLK (output)
< t
SBUSCLK (output)
< t
VBCLKOUT (output)
PLLFO (output)
User's Manual A19069EJ2V0UM
Conditions
< t
>
BCYC
< t
>
< t
WKH1
WKL1
>
< t
>
KR1
KF1
< t
>
BCYC
< t
>
< t
WSKH1
WSKL1
>
< t
>
SKR1
SKF 1
< t
>
VCYC
< t
>
PLCYC
MIN.
MAX.
−
15
0.5T−2.7
0.5T+2.7
0.5T−2.7
0.5T+2.7
3.3
3.3
0.5T−2.1
0.5T+2.1
0.5T−2.1
0.5T+2.1
1.85
1.85
−
10
−
5
>
>
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
17
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