N-Wire Interface Pins; Trace Interface - Renesas PFESiP/V850EP1 User Manual

1.7.9 N-Wire interface pins

(1) Trace interface

The access timing of the trace interface is shown below.
Parameter
TRCDATA output delay time (from TRCCLK ↑ )
TRCEND output delay time (from TRCCLK ↑ )
Note The data output timing of TRCDATA0-TRCDATA7 or TRCEND can be output at the both rising and falling
edges of TRCCLK. It also can be output at the falling edge of TRCCLK. When the timing is output at the
falling edge of TRCCLK, each output delay time is the same as that of the timing output at the rising edge of
TRCCLK. However, the TRCCLK edge for reference differs.
Remark t CPCLK cycle
:
CCLK
TRCCLK (output)
TRCDATA0-
TRCDATA7 (output)
TRCEND (output)
CHAPTER 1 PRODUCT SPECIFCATIONS
Table 1-23. Trace Interface
Symbol
Note
t
DTRCDATA
Note
t
DTRCEND
Figure 1-28. Trace Interface
< t >
DTRCDATA
< t
DTRCEND
User's Manual A19069EJ2V0UM
MIN.
0.0 t
CCLK
0.0 t
CCLK
>
MAX. Unit
× 0.5 + 3.5
ns
× 0.5 + 3.5
ns
47