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2.2 Electrical Specifications
2.2.1 Recommended operating range
Parameter
Oscillation Block Input Frequency
Input Frequency
PFD Input Frequency
Input Duty
Multiple Rate
Frequency Division Ratio Setting
2.2.2 Electrical specifications
Parameter
VCO Output Frequency
Output Frequency
Output Duty
Output Period Jitter
Multiple Rate
Modulation Period
Frequency Modulation Rate f
Remark
The PFD input frequency is an output frequency of the M divider. Refer to 2.1 Block Diagram.
52
CHAPTER 2 INTERNAL SSCG-PLL CHARACTERISTICS
Symbol
Conditions
f
osc
f
std
f
f
= f
/ m
pfd
pfd
std
I
duty
MULT = n / m / p
MULT
m
n
p
Symbol
Conditions
× n/m
f
f
= f
vco
vco
std
× n/m/p
f
f
= f
out
out
std
−
duty
−
t
pj
MULT
MULT = n/m/p
f
PLL13-PLL12(SSMDL1-SSMDL0)= 00
mod
PLL13-PLL12(SSMDL1-SSMDL0)= 01
PLL13-PLL12(SSMDL1-SSMDL0)= 10
PLL13-PLL12(SSMDL1-SSMDL0)= 11
PLL16-PLL14(SSADJ2-SSADJ0)= 000
dit
PLL16-PLL14(SSADJ2-SSADJ0)= 001
PLL16-PLL14(SSADJ2-SSADJ0)= 010
PLL16-PLL14(SSADJ2-SSADJ0)= 011
PLL16-PLL14(SSADJ2-SSADJ0)= 100
PLL16-PLL14(SSADJ2-SSADJ0)= 101
User's Manual A19069EJ2V0UM
MIN.
−
2.0
−
2.0
1.0
−
30
0.182
−
2
−
93
−
1
MIN.
TYP
100
25
47
− 150
0.182
20
30
40
50
− 0.5
− 1.0
− 2.0
− 3.0
− 4.0
− 5.0
MAX.
Unit
50.0
MHz
200.0
MHz
2.0
MHz
%
70
−
50
−
128
100
−
4
−
MAX
Unit
Remark
200
MHz
200
MHz
≤ 0.2pF
53
%
C
L
Fixed frequency mode
150
Ps
−
50
kHz
kHz
kHz
kHz
%
The settings are
performed without
%
modulation in the
%
setting conditions
%
other than those in
%
the left column.
%
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