Pllm0-Pllm6, Plln0-Plln2, Pllp0-Pllp1 (Pllm, N, P-Counter Select) - Renesas PFESiP/V850EP1 User Manual

2.3.1 PLLM0-PLLM6, PLLN0-PLLN2, PLLP0-PLLP1 (PLLM, N, P-counter select)

These pins set the multiplication factor of an internal PLL.
PLLM0 to PLLM6, and PLLP0 and PLLP1 are directly connected to AAPLSCGH of the internal PLL.
PLLN0 to PLLN2 are connected to AAPLSCGH, while 92 is added to them, because the input range of AAPLSCGH
is 92 to 99 in decimal form.
The multiple rates are calculated by the following formula:
m = PLLM0 to PLLM6 setting value (0 to 127) + 1
n = PLLN0 to PLLN2 setting value (0 to 7) + 92 + 1 : 93 to 100
PLLP0 to PLLP1 setting value
p = 2
Multiple rate = n/m/p
The following specifications are satisfied in AAPLSCGH.
Parameter
Input Frequency
PFD Input Frequency
VCO Output Frequency
Output Frequency
Input Duty
multiple rate
PLL11 PLL10
PLLP1 PLLP0
0 0 1
0 1 2
1 0 4
1 1 Through mode
Furthermore, when PLLM0 to PLLM6 are all set to low level, and PLLP0 and PLLP1 are both set to high level, these
low- and high-level settings being prohibited, both of these PLL settings are set to through mode.
54
CHAPTER 2 INTERNAL SSCG-PLL CHARACTERISTICS
Table 2-1. PLL Operating Conditions
Symbol Formula
−
f
std
f f = f / m
pfd pfd std
f f = f × n / m
vco vco std
= f × n / m / p
f f
out
out std
−
I
duty
MULT = n / m / p
MULT
p PLL Output Frequency [MHz]
100 to 200
50 to 100
25 to 50
Through mode
User's Manual A19069EJ2V0UM
: 2 to 128
: 1, 2, 4
MIN.
2.0
1.0
100
25
30
0.182
MAX Unit
200 MHz
2.0 MHz
200 MHz
200 MHz
70 %
−
50