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(a) Base access timing (SRAM, external ROM, external I/O)
Figure 1-13. Base Access Timing (SRAM, External ROM, External I/O)
SBUSCLK (output)
SA0-SA20, SCSZ0-SCSZ3 (output)
SBCYSTZ (output)
SRDZ, SIORDZ (output) (read)
SWRZ0-SWRZ1, SWRSTBZ, SIOWRZ
(output) (write)
SD0-SD15 (I/O) (read)
SD0-SD15 (I/O) (write)
SWAITZ (input)
Remarks 1. Timing when the number of waits set by the DWC0 and DWC1 registers is 0.
2. Broken lines indicate high impedance.
CHAPTER 1 PRODUCT SPECIFCATIONS
T1
<t
>
DKA
<t
>
DKBSL
<t
<t
>
DKRDH
< t
>
< t
>
DKWRH
DKWRL
< t
>
HKOD
< t
>
DKOD
< t
< t
>
SKW
User's Manual A19069EJ2V0UM
TW
T2
<t
>
< t
D KBSH
>
DKRDL
< t
>
DKRDH
< t
DKWRH
< t
>
SKID
>
< t
>
HKW
HKW
< t
>
SKW
< t
>
DKA
>
DKBSL
< t
>
DKRDL
>
< t
>
DKWRL
< t
>
HKID
< t
>
HKOD
33
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