Bus Hold Timing - Renesas PFESiP/V850EP1 User Manual

(2) Bus hold timing

Parameter
SHLDRQZ setup time (to SBUSCLK ↑ )
SHLDRQZ hold time (from SBUSCLK ↑ )
Delay time from SBUSCLK ↑ to SHLDAKZ
SHLDRQZ high-level width
SHLDAKZ low-level width
Delay time from SBUSCLK ↑ to bus float
Delay time from SBUSCLK ↑ to bus output
Delay time from SHLDRQZ ↓ to SHLDAKZ ↓
Delay time from SHLDRQZ ↑ to SHLDAKZ ↑
Remark t SBUSCLK cycle
BCLK:
CHAPTER 1 PRODUCT SPECIFCATIONS
Table 1-16. Bus Hold Timing
Symbol MIN.
t 3.8
SHRK
t 2.0
HKHR
t 1.5
DKHA
t 5.8 + t
WHQH
− 9.5 + t
t
WHAL
t 1.5
DKCF
t 1.5
DHAC
t 1.5 × t
DHQHA1
0.5 × t
t
DHQHA2
User's Manual A19069EJ2V0UM
MAX.
BCLK
BCLK
BCLK
3 × t
BCLK BCLK
Unit
−
ns
−
ns
11.0 ns
− ns
−
ns
−
ns
13.0 ns
− ns
+ 3.8
ns
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